Abstract: A chip package structure and a method for fabricating the same are provided. The chip package structure includes a conductive substrate, a chip, a molding layer and a package cover. The conductive substrate has first and second board surfaces opposite to each other, and a die-bonding region is defined on the first board surface. The chip is disposed on the first board and located in the die-bonding region, and is electrically connected to the conductive substrate. The molding layer is disposed on the first board surface and surrounds the die-bonding region and the chip. The package cover is disposed on the molding layer, and the package cover, the molding layer and the conductive substrate jointly define an enclosed space surrounding the chip. Two of the conductive substrate, the molding layer and the package cover are connected to each other through a mortise-tenon joint structure.