Patents by Inventor Dong-Ryul Ryu
Dong-Ryul Ryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200062957Abstract: Provided is a polyamide-based composite resin composition which includes 30 to 80 wt % of a polyamide-based resin; 5 to 59 wt % of m-xylenediamine (MXD)-based modified nylon; 10 to 50 wt % of thermoplastic olefin rubber including a maleic anhydride-grafted ethylene-octene copolymer, a maleic anhydride-grafted ethylene-propylene-diene monomer, or a mixture thereof; 0.5 to 10 wt % of clay; and 0.01 to 5 wt % of carbon nanotubes (CNTs). According to the present invention, the polyamide-based composite resin composition is easily subjected to blow molding, is excellent in mechanical properties such as low-temperature impact strength and tensile strength, and is also capable of significantly enhancing a gas barrier property.Type: ApplicationFiled: October 20, 2017Publication date: February 27, 2020Applicants: Shinil Chemical Industry Co., Ltd., Korea Fuel Tech CorporationInventors: Keum-Suk Seo, Dong Ryul Ryu, Bo Ram Kwon
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Patent number: 9652324Abstract: A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.Type: GrantFiled: December 27, 2015Date of Patent: May 16, 2017Assignee: Samsung Electronics Co., Ltd.Inventor: Dong-Ryul Ryu
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Publication number: 20160132389Abstract: A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.Type: ApplicationFiled: December 27, 2015Publication date: May 12, 2016Inventor: Dong-Ryul Ryu
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Patent number: 9223650Abstract: A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.Type: GrantFiled: November 17, 2014Date of Patent: December 29, 2015Assignee: Samsung Electronics Co., Ltd.Inventor: Dong-Ryul Ryu
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Publication number: 20150067450Abstract: A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.Type: ApplicationFiled: November 17, 2014Publication date: March 5, 2015Inventor: Dong-Ryul Ryu
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Patent number: 8917565Abstract: A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.Type: GrantFiled: March 14, 2012Date of Patent: December 23, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Dong-Ryul Ryu
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Patent number: 8582392Abstract: A non-volatile memory device is operated by outputting data in response to an alternating sequence of first and second edges of a read control signal, respectively. A determination is made whether the read control signal and a write control signal are in synchronization at one of the first edges. Output of the data is stopped at the second edge that follows the one of the first edges of the read control signal if the read control signal and the write control signal are in synchronization at the one of the first edges.Type: GrantFiled: November 1, 2011Date of Patent: November 12, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Dong-ryul Ryu
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Publication number: 20120173806Abstract: A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.Type: ApplicationFiled: March 14, 2012Publication date: July 5, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Dong-Ryul Ryu
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Patent number: 8159889Abstract: A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.Type: GrantFiled: June 25, 2009Date of Patent: April 17, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Dong-Ryul Ryu
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Patent number: 8145867Abstract: A non-volatile memory device is operated by outputting data in response to an alternating sequence of first and second edges of a read control signal, respectively. A determination is made whether the read control signal and a write control signal are in synchronization at one of the first edges. Output of the data is stopped at the second edge that follows the one of the first edges of the read control signal if the read control signal and the write control signal are in synchronization at the one of the first edges.Type: GrantFiled: November 24, 2004Date of Patent: March 27, 2012Assignee: Samsung Electronics Co., Ltd.Inventor: Dong-ryul Ryu
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Publication number: 20120047389Abstract: A non-volatile memory device is operated by outputting data in response to an alternating sequence of first and second edges of a read control signal, respectively. A determination is made whether the read control signal and a write control signal are in synchronization at one of the first edges. Output of the data is stopped at the second edge that follows the one of the first edges of the read control signal if the read control signal and the write control signal are in synchronization at the one of the first edges.Type: ApplicationFiled: November 1, 2011Publication date: February 23, 2012Inventor: Dong-ryul Ryu
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Publication number: 20090265513Abstract: A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.Type: ApplicationFiled: June 25, 2009Publication date: October 22, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Dong-Ryul RYU
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Patent number: 7584304Abstract: We describe and claim an improved non-volatile memory storage device including an interface select switch and associated method. The device comprises a non-volatile memory, and an interface unit including a plurality of storage interfaces, the interface unit to select a storage interface from the plurality of storage interfaces responsive to a selection signal, where the non-volatile memory to exchange data with a host external to the device via the selected storage interface. In an embodiment, the selected storage interface is an ATA storage interface to convert the exchanged data in accordance with an ATA protocol when selected responsive to the selection signal. In another embodiment, the selected storage interface is a SATA storage interface to convert the exchanged data in accordance with a SATA protocol when selected responsive to the selection signal.Type: GrantFiled: July 13, 2005Date of Patent: September 1, 2009Assignee: Samsung ElectronicsInventors: Jeong-Woo Lee, Dong-Ryul Ryu
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Patent number: 7523274Abstract: A data storage device includes a memory block, a data classification unit, and a memory control unit. The memory block includes a high-speed nonvolatile memory and a low-speed nonvolatile memory, wherein a data access speed of the high-speed nonvolatile memory is greater than a data access speed of the low-speed nonvolatile memory. The data classification unit classifies the externally input data into data groups including busy data and free data, where the busy data has greater access frequency than the free data. The memory control unit configured to store the externally input data classified by the data classification unit as busy data in the high-speed nonvolatile memory, and to store the externally input data classified by the data classification unit as free data in the low-speed nonvolatile memory.Type: GrantFiled: December 29, 2005Date of Patent: April 21, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Ryul Ryu, Jong-Soo Lee
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Publication number: 20070106836Abstract: A semiconductor solid state disk control device includes a flash interface configured to interface with the flash memory. The control device also includes a host interface configured to interface with the host. The control device also includes a first clock generator configured to generate a first driving clock to the host interface. The control device also includes a second clock generator configured to generate a second driving clock to the flash interface independent of the first clock generator.Type: ApplicationFiled: November 9, 2006Publication date: May 10, 2007Inventors: Jeong-Woo Lee, Dong-Ryul Ryu
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Publication number: 20060248259Abstract: A data storage device includes a memory block, a data classification unit, and a memory control unit. The memory block includes a high-speed nonvolatile memory and a low-speed nonvolatile memory, wherein a data access speed of the high-speed nonvolatile memory is greater than a data access speed of the low-speed nonvolatile memory. The data classification unit classifies the externally input data into data groups including busy data and free data, where the busy data has greater access frequency than the free data. The memory control unit configured to store the externally input data classified by the data classification unit as busy data in the high-speed nonvolatile memory, and to store the externally input data classified by the data classification unit as free data in the low-speed nonvolatile memory.Type: ApplicationFiled: December 29, 2005Publication date: November 2, 2006Inventors: Dong-Ryul Ryu, Jong-Soo Lee
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Publication number: 20060152981Abstract: A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.Type: ApplicationFiled: December 19, 2005Publication date: July 13, 2006Inventor: Dong-Ryul Ryu
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Publication number: 20060069820Abstract: We describe and claim an improved non-volatile memory storage device including an interface select switch and associated method. The device comprises a non-volatile memory, and an interface unit including a plurality of storage interfaces, the interface unit to select a storage interface from the plurality of storage interfaces responsive to a selection signal, where the non-volatile memory to exchange data with a host external to the device via the selected storage interface. In an embodiment, the selected storage interface is an ATA storage interface to convert the exchanged data in accordance with an ATA protocol when selected responsive to the selection signal. In another embodiment, the selected storage interface is a SATA storage interface to convert the exchanged data in accordance with a SATA protocol when selected responsive to the selection signal.Type: ApplicationFiled: July 13, 2005Publication date: March 30, 2006Inventors: Jeong-Woo Lee, Dong-Ryul Ryu
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Publication number: 20060023499Abstract: A non-volatile memory device is operated by outputting data in response to an alternating sequence of first and second edges of a read control signal, respectively. A determination is made whether the read control signal and a write control signal are in synchronization at one of the first edges. Output of the data is stopped at the second edge that follows the one of the first edges of the read control signal if the read control signal and the write control signal are in synchronization at the one of the first edges.Type: ApplicationFiled: November 24, 2004Publication date: February 2, 2006Inventor: Dong-ryul Ryu
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Patent number: 6888216Abstract: The present invention discloses a circuit having a make-link type fuse. The circuit comprising a first make-link type fuse connected between a gate of a transistor and a first supply voltage.Type: GrantFiled: August 30, 2002Date of Patent: May 3, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Seok Lee, Young-Kug Moon, Dong-Ryul Ryu