Abstract: A digital pulse width modulator leverages clock frequency to achieve very fine duty cycle resolution by using a constant number of time slots for each state of a pulse signal and varying the number of time slots in a switching cycle within acceptable limits for variation of the switching cycle frequency or by using two relatively low frequency clocks of slightly differing frequency and selecting pulse leading and trailing edges in accordance with pulses output therefrom. A fine resolution of duty cycle adjustment can thus be provided corresponding to a much higher effective clock frequency than is actually used; allowing improvement of efficiency of clock and switching circuits, particularly in switching voltage regulator applications.

Abstract: A digital pulse width modulator leverages clock frequency to achieve very fine duty cycle resolution by using a constant number of time slots for each state of a pulse signal and varying the number of time slots in a switching cycle within acceptable limits for variation of the switching cycle frequency or by using two relatively low frequency clocks of slightly differing frequency and selecting pulse leading and trailing edges in accordance with pulses output therefrom. A fine resolution of duty cycle adjustment can thus be provided corresponding to a much higher effective clock frequency than is actually used; allowing improvement of efficiency of clock and switching circuits, particularly in switching voltage regulator applications.

Abstract: A CMOS differential operational amplifier has a fully differential structure to improve the output swing and a cascode amplification structure to improve the operating speed. This amplifier includes: a differential input stage 21 which receives differential input voltage signals and converts the input voltage signals into current signals; a cascode output stage 22 which amplifies the current signals from the differential input stage 21 and converts them into high gain output voltage signals; and a common-mode feedback circuit(CMF) 23 which makes a common-mode voltage signal of the output voltage signals equal to a reference voltage signal. To the output ports of the cascode output stage 22, a load capacitor (C.sub.L) 24 is connected.