Patents by Inventor Dong Seong Oh
Dong Seong Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11081419Abstract: A method to manufacture a semiconductor package includes: preparing a metal substrate; attaching semiconductor dies to the metal substrate at an interval; attaching a bonding film to the semiconductor dies; applying a mold material on the semiconductor dies and the metal substrate, and curing the mold material to form a mold member; grinding the mold member and the metal substrate to a thickness; removing the bonding film; attaching a redistribution layer to the semiconductor dies; and cutting between the semiconductor dies.Type: GrantFiled: March 6, 2019Date of Patent: August 3, 2021Assignee: MagnaChip Semiconductor, Ltd.Inventors: Jae Sik Choi, Dong Seong Oh, Si Hyeon Go
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Patent number: 10431530Abstract: A power semiconductor module includes: a substrate including first, second, and third metal patterns separated from each other, a semiconductor element located on the substrate, a lead frame located on the substrate and including first, second, third, and fourth bodies; a first terminal connected to the first body, a second terminal connected to the second body, and a third common terminal that connects the third body and the fourth body, wherein a length of the third common terminal is longer than that of the first and second terminals.Type: GrantFiled: December 5, 2017Date of Patent: October 1, 2019Assignee: MagnaChip Semiconductor, Ltd.Inventors: Jae Sik Choi, Si Hyeon Go, Jun Young Heo, Moon Taek Sung, Dong Seong Oh
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Patent number: 10347565Abstract: A multi-chip package of power semiconductor includes a lead frame, a first segment group, a second segment group, a first power semiconductor chip and a second power semiconductor chip. The lead frame includes a first segment group having a first gate segment, a first source segment, and a first drain segment that are separated from each other. The second segment group has a second gate segment, a second source segment, and a second drain segment that are separated from each other. The first power semiconductor chip is formed on the first segment group. The second power semiconductor chip is formed on the second segment group. The first source segment is physically connected to the second drain segment.Type: GrantFiled: January 2, 2018Date of Patent: July 9, 2019Assignee: MagnaChip Semiconductor, Ltd.Inventors: Si Hyeon Go, Jae Sik Choi, Myung Ho Park, Dong Seong Oh, Beom Su Kim
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Publication number: 20190199191Abstract: A high voltage start-up circuit includes a power supply terminal configured to supply power, a latch unit connected to the power supply terminal and comprising a first P-type Metal-Oxide-Semiconductor (PMOS) transistor, a first N-type metal-oxide semiconductor (NMOS) transistor connected to the first PMOS transistor, a second PMOS transistor, and a second NMOS transistor connected to the second PMOS transistor, wherein the transistors form a latch structure, a charge sharing unit comprising a first capacitor configured to supply a first voltage to a drain of the second PMOS transistor and a second capacitor configured to supply a second voltage to a drain of the first PMOS transistor, and a switching unit configured to form a current path that charges an external capacitor using a voltage supplied from the power supply terminal as a power voltage, based on the first voltage and the second voltage.Type: ApplicationFiled: August 23, 2018Publication date: June 27, 2019Applicant: Magnachip Semiconductor, Ltd.Inventors: Zhi Yuan CUI, Sang Hoon JUNG, Dong Seong OH, Byung Ki KIM
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Publication number: 20190198415Abstract: A method to manufacture a semiconductor package includes: preparing a metal substrate; attaching semiconductor dies to the metal substrate at an interval; attaching a bonding film to the semiconductor dies; applying a mold material on the semiconductor dies and the metal substrate, and curing the mold material to form a mold member; grinding the mold member and the metal substrate to a thickness; removing the bonding film; attaching a redistribution layer to the semiconductor dies; and cutting between the semiconductor dies.Type: ApplicationFiled: March 6, 2019Publication date: June 27, 2019Applicant: MagnaChip Semiconductor, Ltd.Inventors: Jae Sik CHOI, Dong Seong OH, Si Hyeon GO
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Patent number: 10333381Abstract: A high voltage start-up circuit includes a power supply terminal configured to supply power, a latch unit connected to the power supply terminal and comprising a first P-type Metal-Oxide-Semiconductor (PMOS) transistor, a first N-type metal-oxide semiconductor (NMOS) transistor connected to the first PMOS transistor, a second PMOS transistor, and a second NMOS transistor connected to the second PMOS transistor, wherein the transistors form a latch structure, a charge sharing unit comprising a first capacitor configured to supply a first voltage to a drain of the second PMOS transistor and a second capacitor configured to supply a second voltage to a drain of the first PMOS transistor, and a switching unit configured to form a current path that charges an external capacitor using a voltage supplied from the power supply terminal as a power voltage, based on the first voltage and the second voltage.Type: GrantFiled: August 23, 2018Date of Patent: June 25, 2019Assignee: MagnaChip Semiconductor, Ltd.Inventors: Zhi Yuan Cui, Sang Hoon Jung, Dong Seong Oh, Byung Ki Kim
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Patent number: 10269677Abstract: A method to manufacture a semiconductor package includes: preparing a metal substrate; attaching semiconductor dies to the metal substrate at an interval; attaching a bonding film to the semiconductor dies; applying a mold material on the semiconductor dies and the metal substrate, and curing the mold material to form a mold member; grinding the mold member and the metal substrate to a thickness; removing the bonding film; attaching a redistribution layer to the semiconductor dies; and cutting between the semiconductor dies.Type: GrantFiled: April 19, 2017Date of Patent: April 23, 2019Assignee: MagnaChip Semiconductor, Ltd.Inventors: Jae Sik Choi, Dong Seong Oh, Si Hyeon Go
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Publication number: 20180358285Abstract: A multi-chip package of power semiconductor includes a lead frame, a first segment group, a second segment group, a first power semiconductor chip and a second power semiconductor chip. The lead frame includes a first segment group having a first gate segment, a first source segment, and a first drain segment that are separated from each other. The second segment group has a second gate segment, a second source segment, and a second drain segment that are separated from each other. The first power semiconductor chip is formed on the first segment group. The second power semiconductor chip is formed on the second segment group. The first source segment is physically connected to the second drain segment.Type: ApplicationFiled: January 2, 2018Publication date: December 13, 2018Applicant: MagnaChip Semiconductor, Ltd.Inventors: Si Hyeon GO, Jae Sik CHOI, Myung Ho PARK, Dong Seong OH, Beom Su KIM
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Patent number: 10020790Abstract: A composite electronic component includes: a power stabilization unit including a capacitor and an inductor connected to each other in series and configured to rectify input voltage to generate output voltage; and a switch unit including a first switch connected to the capacitor in parallel and a second switch connected to the inductor in parallel.Type: GrantFiled: December 16, 2015Date of Patent: July 10, 2018Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: In Wha Jeong, Dong Seong Oh, Hugh Kim
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Publication number: 20180151465Abstract: A method to manufacture a semiconductor package includes: preparing a metal substrate; attaching semiconductor dies to the metal substrate at an interval; attaching a bonding film to the semiconductor dies; applying a mold material on the semiconductor dies and the metal substrate, and curing the mold material to form a mold member; grinding the mold member and the metal substrate to a thickness; removing the bonding film; attaching a redistribution layer to the semiconductor dies; and cutting between the semiconductor dies.Type: ApplicationFiled: April 19, 2017Publication date: May 31, 2018Applicant: MagnaChip Semiconductor, Ltd.Inventors: Jae Sik CHOI, Dong Seong OH, Si Hyeon GO
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Publication number: 20180102309Abstract: A power semiconductor module includes: a substrate including first, second, and third metal patterns separated from each other, a semiconductor element located on the substrate, a lead frame located on the substrate and including first, second, third, and fourth bodies; a first terminal connected to the first body, a second terminal connected to the second body, and a third common terminal that connects the third body and the fourth body, wherein a length of the third common terminal is longer than that of the first and second terminals.Type: ApplicationFiled: December 5, 2017Publication date: April 12, 2018Applicant: Magnachip Semiconductor, Ltd.Inventors: Jae Sik CHOI, Si Hyeon Go, Jun Young Heo, Moon Taek Sung, Dong Seong Oh
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Patent number: 9893000Abstract: A power semiconductor module includes: a substrate including first, second, and third metal patterns separated from each other, a semiconductor element located on the substrate, a lead frame located on the substrate and including first, second, third, and fourth bodies; a first terminal connected to the first body, a second terminal connected to the second body, and a third common terminal that connects the third body and the fourth body, wherein a length of the third common terminal is longer than that of the first and second terminals.Type: GrantFiled: August 23, 2016Date of Patent: February 13, 2018Assignee: Magnachip Semiconductor, Ltd.Inventors: Jae Sik Choi, Si Hyeon Go, Jun Young Heo, Moon Taek Sung, Dong Seong Oh
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Publication number: 20170287821Abstract: A power semiconductor module includes: a substrate including first, second, and third metal patterns separated from each other, a semiconductor element located on the substrate, a lead frame located on the substrate and including first, second, third, and fourth bodies; a first terminal connected to the first body, a second terminal connected to the second body, and a third common terminal that connects the third body and the fourth body, wherein a length of the third common terminal is longer than that of the first and second terminals.Type: ApplicationFiled: August 23, 2016Publication date: October 5, 2017Applicant: Magnachip Semiconductor, Ltd.Inventors: Jae Sik CHOI, Si Hyeon GO, Jun Young HEO, Moon Taek SUNG, Dong Seong OH
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Patent number: 9647580Abstract: A wireless signal transmitting apparatus, includes: a piezoelectric harvester configured to generate electrical energy responsive to user switch manipulation; and, a wireless communication circuit configured to generate wireless signals from the electrical energy and wirelessly transmit the wireless signals to an external wireless power receiving device.Type: GrantFiled: March 18, 2016Date of Patent: May 9, 2017Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: In Wha Jeong, Dong Seong Oh, Hugh Kim
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Publication number: 20170019038Abstract: A wireless signal transmitting apparatus, includes: a piezoelectric harvester configured to generate electrical energy responsive to user switch manipulation; and, a wireless communication circuit configured to generate wireless signals from the electrical energy and wirelessly transmit the wireless signals to an external wireless power receiving device.Type: ApplicationFiled: March 18, 2016Publication date: January 19, 2017Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: In Wha JEONG, Dong Seong OH, Hugh KIM
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Publication number: 20160189869Abstract: A composite electronic component includes: a power stabilization unit including a capacitor and an inductor connected to each other in series and configured to rectify input voltage to generate output voltage; and a switch unit including a first switch connected to the capacitor in parallel and a second switch connected to the inductor in parallel.Type: ApplicationFiled: December 16, 2015Publication date: June 30, 2016Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: In Wha JEONG, Dong Seong OH, Hugh KIM
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Patent number: 9054601Abstract: Disclosed are a maximum power point tracker, a power conversion controller, a power conversion device having an insulating structure, and a method for tracking maximum power point. The power conversion device includes: a DC/AC converter including a primary DC chopper unit having a primary switch, a transformer, and an AC/AC conversion unit including a secondary switch; a current detector detecting current from an input stage of the DC/AC converter and providing a detected current value; a voltage detector detecting a system voltage from an output stage of the DC/AC converter; and a power conversion controller generating a primary PWM signal to be provided to the primary DC chopper unit and secondary first and second PWM signals, having the mutually opposing phases, to be provided to the AC/AC conversion unit by using the detected current value and the system voltage.Type: GrantFiled: March 15, 2013Date of Patent: June 9, 2015Assignees: SAMSUNG ELECTRO-MECHANICS CO., LTD., SUNGKYUNKWAN UNIVERSITY FOUNDATION FOR CORPORATION COLLABORATIONInventors: Jin Wook Kim, Tae Won Lee, Dong Seong Oh, Yong Hyok Ji, Byoung Kuk Lee, Chung Yuen Won, Jae Hyung Kim, Young Ho Kim
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Publication number: 20140035477Abstract: There are provided a single stage forward-flyback converter, and a power supply apparatus capable of increasing power factor correction and power conversion efficiency. The single stage forward-flyback converter includes: a forward converter unit including a transformer having a primary winding receiving input power and a first secondary winding magnetically coupled to the primary winding to receive power induced thereto, and converting the power in a forward scheme; and a flyback converter unit sharing the transformer, including a second secondary winding, and converting the power in a flyback scheme, wherein the forward converter unit is selectively operated according to a voltage level of the input power.Type: ApplicationFiled: August 2, 2013Publication date: February 6, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Sang Kyoo HAN, Yoon CHOI, Min Ha HWANG, Hong Sun PARK, Byoung Woo RYU, Sung Cheol KIM, Dong Seong OH
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Publication number: 20140035485Abstract: There is provided a single-stage forward-flyback converter capable of increasing power factor and power conversion efficiency while performing power factor correction and constant current control in a single-stage circuit. The converter includes: a power converting unit including a transformer having a primary winding receiving input power and a secondary winding magnetically coupled to the primary winding to receive power induced thereto, and converting the input power in a forward scheme and a flyback scheme; a balancing unit maintaining balance between a power level by the forward scheme of the power converting unit and a power level by the flyback scheme thereof; and a path providing unit clamping the power by the forward scheme of the power converting unit and the power by the flyback scheme thereof to provide a power transfer path, wherein the power converting unit selectively operates the forward scheme according to a voltage level of input power.Type: ApplicationFiled: August 2, 2013Publication date: February 6, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Sang Kyoo HAN, Min Ha HWANG, Yoon CHOI, Hong Sun PARK, Byoung Woo RYU, Sung Cheol KIM, Dong Seong OH
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Patent number: 8598741Abstract: There are disclosed a photovoltaic and fuel cell (PV-FC) hybrid generation system using a single converter and a single inverter, and a method of controlling the same. The PV-FC hybrid generation system includes a DC/DC converter unit converting an FC output voltage from a fuel cell, converting chemical energy into electrical energy, into a preset voltage, a DC link unit commonly connecting an output terminal of a photovoltaic cell, converting the sunlight into electrical energy, and an output terminal of the DC/DC converter unit, and linking the converted FC output voltage from the DC/DC converter unit with a PV output voltage from the photovoltaic cell to thereby generate a DC voltage, and a DC/AC inverter unit converting the DC voltage from the DC link unit into a preset AC voltage. Furthermore, a method of controlling the PV-FC hybrid generation system is proposed.Type: GrantFiled: December 21, 2009Date of Patent: December 3, 2013Assignees: Samsung Electro-Mechanics Co, Ltd., Sungkyunkwan University Foundation for Corporate CollaborationInventors: Jin Wook Kim, Byoung Kuk Lee, Jong Soo Kim, Gyu Yeong Choe, Jong Sun Kim, Il Woon Lee, Jae Sun Won, Jong Hae Kim, Dong Seong Oh