Abstract: Devices and methods for detecting and correcting duty cycles are described. An input switching unit is configured to perform at least one of an operation of outputting differential input signals as a first combination of first and second output signals and an operation of outputting the differential input signals as a second combination of the first and second output signals, according to one of a plurality of control signals. A comparator is configured to receive the first output signal through a first input terminal thereof, to receive the second output signal through a second input terminal thereof, to generate duty detection signals by comparing the signal of the first input terminal and the signal of the second input terminal according to at least another one of the plurality of control signals, and to adjust an offset of at least one of the first input terminal and the second input terminal.

Abstract: Devices and methods for detecting and correcting duty cycles are described. An input switching unit is configured to perform at least one of an operation of outputting differential input signals as a first combination of first and second output signals and an operation of outputting the differential input signals as a second combination of the first and second output signals, according to one of a plurality of control signals. A comparator is configured to receive the first output signal through a first input terminal thereof, to receive the second output signal through a second input terminal thereof, to generate duty detection signals by comparing the signal of the first input terminal and the signal of the second input terminal according to at least another one of the plurality of control signals, and to adjust an offset of at least one of the first input terminal and the second input terminal.

Abstract: Devices and methods for detecting and correcting duty cycles are described. An input switching unit is configured to perform at least one of an operation of outputting differential input signals as a first combination of first and second output signals and an operation of outputting the differential input signals as a second combination of the first and second output signals, according to one of a plurality of control signals. A comparator is configured to receive the first output signal through a first input terminal thereof, to receive the second output signal through a second input terminal thereof, to generate duty detection signals by comparing the signal of the first input terminal and the signal of the second input terminal according to at least another one of the plurality of control signals, and to adjust an offset of at least one of the first input terminal and the second input terminal.

Abstract: Devices and methods for detecting and correcting duty cycles are described. An input switching unit is configured to perform at least one of an operation of outputting differential input signals as a first combination of first and second output signals and an operation of outputting the differential input signals as a second combination of the first and second output signals, according to one of a plurality of control signals. A comparator is configured to receive the first output signal through a first input terminal thereof, to receive the second output signal through a second input terminal thereof, to generate duty detection signals by comparing the signal of the first input terminal and the signal of the second input terminal according to at least another one of the plurality of control signals, and to adjust an offset of at least one of the first input terminal and the second input terminal.

Abstract: An electronic device is provided. A buffer circuit, having improved reliability according to the present disclosure, includes a pause detector and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a toggle state or a pause state. The output signal controller generates an output signal based on the input signal and controls a duty cycle of the output signal according to the pause signal.

Abstract: An electronic device is provided. A buffer circuit, performing an optimized operation according to the present disclosure, includes a pause detector, a toggle detector, and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a pause state. The toggle detector receives the input signal and the pause signal and generates a toggle signal which indicates whether the input signal is in a toggle state. The output signal controller generates an output signal which controls input buffer circuits according to the toggle signal.

Abstract: An electronic device is provided. A buffer circuit, having improved reliability according to the present disclosure, includes a pause detector and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a toggle state or a pause state. The output signal controller generates an output signal based on the input signal and controls a duty cycle of the output signal according to the pause signal.

Abstract: An electronic device is provided. A buffer circuit, performing an optimized operation according to the present disclosure, includes a pause detector, a toggle detector, and an output signal controller. The pause detector receives an input signal and generates a pause signal which indicates whether the input signal is in a pause state. The toggle detector receives the input signal and the pause signal and generates a toggle signal which indicates whether the input signal is in a toggle state. The output signal controller generates an output signal which controls input buffer circuits according to the toggle signal.

Abstract: A capacitor is provided. The capacitor includes first and second electrode layers facing each other, a first conductive pattern disposed between the first and second electrode layers, the first conductive pattern forming a closed loop in plan view, a second conductive pattern disposed within an inner space surrounded by the closed loop of the first conductive pattern, the second conductive pattern being spaced from the first conductive pattern, and a first contact plug passing through the second conductive pattern to contact the first and second electrode layers.