Abstract: The present invention relates to a low-odor thermoplastic resin composition. In particular the resin of the resin composition is prepared by a new bulk polymerization process that is used to reduce the characteristic chemical odor in new cars. The resin minimizes the use of the resin prepared by the conventional emulsion polymerization process, N-substituted maleimide and ?-alkylstyrene-based heat-resistant materials which are used to improve heat resistance and the molecular weight of the matrix of the thermoplastic composition. The resin is also improves impact strength, thereby having reduced characteristic chemical odor, while having superior impact strength and heat resistance.

Abstract: A structure and method of fabrication of a semiconductor device, where a stress layer is formed over a MOS transistor to put either tensile stress or compressive stress on the channel region. The parameters such as the location and area of the contact hole thru the stress layer are chosen to produce a desired amount of stress to improve device performance. In an example embodiment for a tensile stress layer, the PMOS S/D contact area is larger than the NMOS S/D contact area so the tensile stress on the PMOS channel is less than the tensile stress on the NMOS channel. In an example embodiment for a compressive stress layer, the NMOS contact area is larger than the PMOS contact area so that the compressive stress on the NMOS channel is less than the compressive stress on the PMOS channel.

Abstract: A method of fabrication of semiconductor substrate structure comprising the following. A buffer layer is formed on the Si Substrate. We form a SiGe layer on the novel buffer layer. The buffer layer has defects therein so that the buffer layer is oxidized to form a buried isolation layer comprised of silicon oxide and an oxide layer and oxidize the SiGe layer for form a oxide layer. The oxide layer is then removed. An upper semiconductor layer (e.g., Si, SiGe or Ge layer) is epitaxially formed on the SiGe layer. Devices are formed on said an upper semiconductor layer. The buffer layer can be formed by several aspects.

Abstract: A structure and a method of manufacturing a memory devices using nanoncrystals. A first embodiment is characterized as follows. We form a first gate insulator over the substrate. The first gate insulator is comprised of an oxide layer and blocking layer. We form a SiGe layer over the first gate insulator layer. Then we perform an oxidation/anneal process consume the SiGe layer to form Ge nanocrystals7 on the first gate insulator layer and a silicon oxide layer over the first gate insulator layer. We form a gate electrode over the a silicon oxide layer. In a second embodiment, the first gate insulator is comprised of one layer of oxidation blocking material. The blocking layer prevents the oxidation of the substrate during process steps used to form the nanocrystals.

Abstract: An embodiment of fabrication of a variable work function gates in a FUSI device is described. The embodiment uses a work function doping implant to dope the polysilicon to achieve a desired work function. Selective epitaxy growth (SEG) is used to form silicon over the source/drain regions. The doped poly-Si gate is fully silicided to form fully silicided gates that have a desired work function. We provide a substrate having a NMOS region and a PMOS region. We form a gate dielectric layer and a gate layer over said substrate. We perform a (gate Vt) gate layer implant process to implant impurities such as P+, As+, B+, BF2+, N+, Sb+, In+, C+, Si+, Ge+ or Ar+ into the gate layer gate in the NMOS gate regions and said PMOS gate regions. We form a cap layer over said gate layer. We pattern said cap layer, said gate layer and said gate dielectric layer to form a NMOS gate and a PMOS gate. Spacers are formed and S/D regions are formed. A metal is deposited over said substrate surface.

Abstract: Structures and methods of fabricating of a floating gate non-volatile memory device. In a first example embodiment, We form a bottom tunnel layer comprised of a lower oxide tunnel layer and a upper hafnium oxide tunnel layer; a charge storage layer comprised of a tantalum oxide and a top blocking layer preferably comprised of a lower hafnium oxide storage layer and an upper oxide storage layer. We form a gate electrode over the top blocking layer. We pattern the layers to form a gate structure and form source/drain regions to complete the memory device. In a second example embodiment, we form a floating gate non-volatile memory device comprised of: a bottom tunnel layer comprised essentially of silicon oxide; a charge storage layer comprised of a tantalum oxide; a top blocking layer comprised essentially of silicon oxide; and a gate electrode. The embodiments also comprise anneals and nitridation steps.

Abstract: An example method of forming a bitline contact region and bitline contact plug for a memory device using a laser irradiation activation process. An example embodiment comprises: providing a substrate having a logic region and a SONOS memory region. We form in the memory region, a memory transistor comprised of a memory gate dielectric, a memory gate electrode, memory LDD regions, memory spacers on the sidewalls of the memory gate electrode. We then perform a “memory Cell Source Line” implant to form a memory source line in the memory region adjacent to the memory gate electrode. We form silicide over the memory gate electrode and on the memory source line. We form an ILD dielectric layer over the substrate surface. We form a contact opening in the ILD dielectric layer over the memory Drain in the memory area. We etch an opening in the substrate in the drain region adjacent to the memory gate electrode. The opening exposes the memory cell first well and exposes the memory drain on the sidewall of the opening.

Abstract: A method of forming a gate dielectric layer is disclosed. The method comprises the following steps. A substrate is provided having silicon regions containing surfaces upon which gate dielectrics are to be disposed. An oxide is formed over the surfaces. A silicon layer is formed over the oxide layer. A nitridation process is performed. An optional high temperature annealing step may be performed.

Abstract: A method of forming a relaxed silicon—germanium layer for use as an underlying layer for a subsequent, overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon—germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon—germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon—germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon—germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon—germanium layer progresses.

Abstract: A method of forming a relaxed silicon-germanium layer for use as an underlying layer for a subsequent overlying tensile strain silicon layer, has been developed. The method features initial growth of a underlying first silicon-germanium layer on a semiconductor substrate, compositionally graded to feature the largest germanium content at the interface of the first silicon-germanium layer and the semiconductor substrate, with the level of germanium decreasing as the growth of the graded first silicon-germanium layer progresses. This growth sequence allows the largest lattice mismatch and greatest level of threading dislocations to be present at the bottom of the graded silicon-germanium layer, with the magnitude of lattice mismatch and threading dislocations decreasing as the growth of the graded silicon-germanium layer progresses.