Abstract: A method of managing dynamic memory reallocation includes receiving an input address including a block bit part, a tag part, and an index part and communicating the index part to a tag memory array, receiving a tag group communicated by the tag memory array based on the index part, analyzing the tag group based on the block bit part and the tag part and changing the block bit part and the tag part based on a result of the analysis, and outputting an output address including a changed block bit part, a changed tag part, and the index part.

Abstract: The invention relates to an industrial robot having an apparatus for driving an attachable/detachable four-bar link mechanism, comprising: a base frame having a rotating joint for a robot body; a pivot frame which is coupled to the rotating joint and which has a rotating joint; a column frame which is coupled to the rotating joint of the pivot frame, and which has a straight-line joint; a motor arranged in the pivot frame to rotate the column frame; a decelerator attachably/detachably mounted on the rotating joint of the pivot frame or directly on the pivot frame to receive driving force from the motor; and a four-bar link installed between an output shaft of the decelerator and the column frame.

Abstract: A tile binning method including: dividing a scene for rendering a triangle, into a plurality of tiles; determining identification values of tile nodes of each of the tiles; and identifying a tile including an entirety or a part of the triangle from the tiles, based on the identification value of the tile nodes for each of the tiles.

Abstract: A priority determining method and apparatus can reduce a total waiting time of DMA request blocks by granting priority to each of Direct Memory Access (DMA) request blocks transmitting a DMA request signal, based on Data Transfer Amounts (DTAs) of the DMA request blocks and Arrival Times (ATs) of the DMA request signals, counting the number of priority changes of each of DMA request blocks whose priority is changed in the priority granting process, and if a DMA request signal is received from a new DMA request block, determining priorities of the DMA request blocks based on the counted the number of priority changes.

Abstract: In a semiconductor memory device and an internal data transmission method thereof, the device includes a memory controller, a pair of data lines, and a plurality of memory banks. During an internal data transmission operation, the memory controller externally receives and stores a source address and a target address in response to an externally applied command and outputs an internal control signal and an internal address signal using the source address and the target address. The internal control signal includes an internal write signal and an internal read signal. Transmission data is transmitted on the pair of data lines during the internal data transmission operation. The plurality of memory banks read the transmission data stored in a region corresponding to the source address in response to the internal read signal, transmit the transmission data on the pair of data lines, and write the transmission data transmitted on the pair of data lines in response to the internal write signal.

Abstract: An image interpolation method interpolating image information of a point in a space constructed by a plurality of planes. According to the method, a reliable interpolated value can be rapidly obtained by searching for the nearest plane to the point, obtaining information about a plane facing the nearest plane using image information of one or more vertices of the plane facing the nearest plane, and interpolating the image information of the point using the image information of the one or more vertices of the nearest plane and the obtained information about the plane facing the nearest plane.

Abstract: In a semiconductor memory device and an internal data transmission method thereof, the device includes a memory controller, a pair of data lines, and a plurality of memory banks. During an internal data transmission operation, the memory controller externally receives and stores a source address and a target address in response to an externally applied command and outputs an internal control signal and an internal address signal using the source address and the target address. The internal control signal includes an internal write signal and an internal read signal. Transmission data is transmitted on the pair of data lines during the internal data transmission operation. The plurality of memory banks read the transmission data stored in a region corresponding to the source address in response to the internal read signal, transmit the transmission data on the pair of data lines, and write the transmission data transmitted on the pair of data lines in response to the internal write signal.

Abstract: A priority determining method and apparatus can reduce a total waiting time of DMA request blocks by granting priority to each of Direct Memory Access (DMA) request blocks transmitting a DMA request signal, based on Data Transfer Amounts (DTAs) of the DMA request blocks and Arrival Times (ATs) of the DMA request signals, counting the number of priority changes of each of DMA request blocks whose priority is changed in the priority granting process, and if a DMA request signal is received from a new DMA request block, determining priorities of the DMA request blocks based on the counted the number of priority changes.

Abstract: An image interpolation method interpolating image information of a point in a space constructed by a plurality of planes. According to the method, a reliable interpolated value can be rapidly obtained by searching for the nearest plane to the point, obtaining information about a plane facing the nearest plane using image information of one or more vertices of the plane facing the nearest plane, and interpolating the image information of the point using the image information of the one or more vertices of the nearest plane and the obtained information about the plane facing the nearest plane.

Abstract: A tile binning method including: dividing a scene for rendering a triangle, into a plurality of tiles; determining identification values of tile nodes of each of the tiles; and identifying a tile including an entirety or a part of the triangle from the tiles, based on the identification value of the tile nodes for each of the tiles.

Abstract: An apparatus carries out encoding variable length codes (VLCs) represented by variable-length codewords and their lengths, and segmenting variable-length codewords of the VLCs into N-bit segments for the transmission thereof, and, if the length of the last segment of the N-bit segments is shorter than N, inserting bits having the value zero between the last bit of the last segment and a start code with a start code prefix followed by a start code value identifying the type of the start code in order to represent the start of a code sequence such that the first bit of the start code is the most significant bit of a byte. The apparatus comprises a byte alignment unit that operates in response to a byte alignment signal.

Abstract: An apparatus for encoding variable length codes (VLCs) represented by variable-length codewords and their lengths, and segmenting variable-length codewords of the VLCs into fixed-length segments for a transmission thereof, comprises: a lookup table for mapping each of source codes into each of the VLCs to produce each of the variable-length codewords and its length; a first barrel shifter, in response to the length of the present input variable-length codeword, for concatenating a present input variable-length codeword and a concatenated variable-length codeword together; a second barrel shifter, in response to a control signal, for producing a fixed-length segment out of combined inputs of the present input variable-length codeword and the concatenated variable-length codeword; an adder for adding the length of the present input variable-length codeword and an added length to produce a newly added length; and a register for comparing the newly added length with a predetermined number of bits to store the new

Abstract: The present invention provides an IDCT apparatus for performing an IDCT operation on an input signal having a plurality of macroblocks of transformed coefficients and time gaps of variable duration, each of the time gaps being inserted between two successive macroblocks. The IDCT apparatus comprises an IDCT controller for generating a plurality of control signals, two IDCT processors for alternately converting the macroblocks of coefficients in the data signal into macroblocks of inverse transformed coefficients in response to the control signals. The outputs from the two IDCT processors are combined to the final inverse transformed output data signal from the IDCT apparatus.