Patents by Inventor Dong-Su Jang
Dong-Su Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220173561Abstract: Provided are an electric appliance and a method of manufacturing the same, the electric appliance having a smaller size and a reduced overall weight by preventing a fluid from flowing into a space unrelated to a heating component in a state where the fluid fills its case. The electric appliance includes: a case including a first space and a second space communicated to each other; a first component disposed in the first space; a second component disposed in the second space; a connection portion electrically connecting the first component and the second component to each other; and a potting pattern including a resin material and formed in the first space.Type: ApplicationFiled: November 18, 2021Publication date: June 2, 2022Inventors: Young Jun Jang, Hyun Su Kim, Jun Kyu Lee, Pill Ju Kim, Sang Keun Ji, Dong Kyun Ryu
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Publication number: 20220173560Abstract: Provided are an electric appliance and a method of manufacturing the same, the electric appliance having a smaller size and a reduced overall weight by preventing a fluid from flowing into a space unrelated to a heating component in a state where the fluid fills its case. The electric appliance includes: a case including a first space and a second space communicated to each other; a first component disposed in the first space; a second component disposed in the second space; a connection portion electrically connecting the first component and the second component to each other; and a potting pattern including a resin material and formed in the first space.Type: ApplicationFiled: November 18, 2021Publication date: June 2, 2022Inventors: Young Jun Jang, Hyun Su Kim, Jun Kyu Lee, Pill Ju Kim, Sang Keun Ji, Dong Kyun Ryu
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Patent number: 10937471Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.Type: GrantFiled: July 20, 2020Date of Patent: March 2, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Su Jang, Man-Jae Yang, Jeong-Don Ihm, Go-Eun Jung, Byung-Hoon Jeong, Young-Don Choi
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Publication number: 20200349986Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.Type: ApplicationFiled: July 20, 2020Publication date: November 5, 2020Inventors: Dong-Su Jang, Man-Jae Yang, Jeong-Don Ihm, Go-Eun Jung, Byung-Hoon Jeong, Young-Don Choi
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Patent number: 10741225Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.Type: GrantFiled: February 26, 2020Date of Patent: August 11, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Su Jang, Man-Jae Yang, Jeong-Don Ihm, Go-Eun Jung, Byung-Hoon Jeong, Young-Don Choi
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Publication number: 20200194040Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.Type: ApplicationFiled: February 26, 2020Publication date: June 18, 2020Inventors: DONG-SU JANG, MAN-JAE YANG, JEONG-DON IHM, GO-EUN JUNG, BYUNG-HOON JEONG, YOUNG-DON CHOI
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Patent number: 10600454Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.Type: GrantFiled: May 9, 2018Date of Patent: March 24, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-su Jang, Man-jae Yang, Jeong-don Ihm, Go-eun Jung, Byung-hoon Jeong, Young-don Choi
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Publication number: 20190096447Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.Type: ApplicationFiled: May 9, 2018Publication date: March 28, 2019Inventors: DONG-SU JANG, Man-jae YANG, Jeong-don IHM, Go-eun JUNG, Byung-hoon JEONG, Young-don CHOI
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Patent number: 9773566Abstract: A nonvolatile memory device includes a data path; and a FIFO memory including a plurality of registers connected to the data path. The plurality of registers sequentially receive data from the data path in response to data path input clocks and sequentially output the received data to an input/output pad in response to data path output clocks. The data path output clocks are clocks that are generated by delaying the data path input clocks as long as a delay time.Type: GrantFiled: January 11, 2017Date of Patent: September 26, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Su Jang, Taesung Lee
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Publication number: 20170125115Abstract: A nonvolatile memory device includes a data path; and a FIFO memory including a plurality of registers connected to the data path. The plurality of registers sequentially receive data from the data path in response to data path input clocks and sequentially output the received data to an input/output pad in response to data path output clocks. The data path output clocks are clocks that are generated by delaying the data path input clocks as long as a delay time.Type: ApplicationFiled: January 11, 2017Publication date: May 4, 2017Inventors: DONG-SU JANG, TAESUNG LEE
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Patent number: 9576626Abstract: A nonvolatile memory device includes a data path; and a FIFO memory including a plurality of registers connected to the data path. The plurality of registers sequentially receive data from the data path in response to data path input clocks and sequentially output the received data to an input/output pad in response to data path output clocks. The data path output clocks are clocks that are generated by delaying the data path input clocks as long as a delay time.Type: GrantFiled: January 20, 2015Date of Patent: February 21, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Su Jang, Taesung Lee
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Publication number: 20150348605Abstract: A nonvolatile memory device includes a data path; and a FIFO memory including a plurality of registers connected to the data path. The plurality of registers sequentially receive data from the data path in response to data path input clocks and sequentially output the received data to an input/output pad in response to data path output clocks. The data path output clocks are clocks that are generated by delaying the data path input clocks as long as a delay time.Type: ApplicationFiled: January 20, 2015Publication date: December 3, 2015Inventors: DONG-SU JANG, TAESUNG LEE
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Publication number: 20150294977Abstract: A nonvolatile memory device includes a memory cell array including a plurality of cell strings each having a plurality of memory cells stacked in a direction perpendicular to a substrate, and a peripheral circuit region including a plurality of transistors electrically connected to the memory cell array through a plurality of conductive lines. Each of the transistors includes a gate electrode crossing an active region of the substrate in a first direction and source and drain regions in the active region at the opposite sides of the gate electrode. In at least one of the transistors, the number of source contact plugs connected to the source region is different from the number of drain contact plugs connected to the drain region.Type: ApplicationFiled: December 9, 2014Publication date: October 15, 2015Inventors: SANG-LOK KIM, YOUNGJIN JEON, DEVRAJ RAJAGOPAL, DONG-SU JANG, YONGHO CHO
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Patent number: 8243535Abstract: A semiconductor memory device comprises a memory cell configured to output data to a pair of bitlines, a variable delay circuit configured to receive a sense amplifier enable signal, adjust a delay of the sense amplifier enable signal by changing a slope of a delay based on a variable external power supply voltage, and output a delayed sense amplifier enable signal, and a bitline sense amplifier configured to amplify a voltage difference between the pair of bitlines in response to the delayed sense amplifier enable signal and output the amplified voltage difference to a pair of input/output lines.Type: GrantFiled: March 25, 2010Date of Patent: August 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Su Jang, Yong-Ho Cho
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Patent number: 8203904Abstract: A semiconductor memory device and a layout structure of sub-word line control signal generators. The sub-word line control signal generators are configured to supply a sub-word line control signal of a predefined voltage level to a sub-word line driver to enable a sub-word line of a memory cell array. At least two sub-word line control signal generators are disposed, respectively, at edge areas of the memory cell array, to directly supply the sub-word line control signal to one selected sub-word line driver, thereby reducing the power consumption, including for example, VPP voltage. Embodiments of the present invention also reduce the number of VPP power lines, thereby lessening a noise disturbance.Type: GrantFiled: December 8, 2010Date of Patent: June 19, 2012Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Dong-Su Jang, In-Chul Jeong
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Publication number: 20110075505Abstract: A semiconductor memory device and a layout structure of sub-word line control signal generators. The sub-word line control signal generators are configured to supply a sub-word line control signal of a predefined voltage level to a sub-word line driver to enable a sub-word line of a memory cell array. At least two sub-word line control signal generators are disposed, respectively, at edge areas of the memory cell array, to directly supply the sub-word line control signal to one selected sub-word line driver, thereby reducing the power consumption, including for example, VPP voltage. Embodiments of the present invention also reduce the number of VPP power lines, thereby lessening a noise disturbance.Type: ApplicationFiled: December 8, 2010Publication date: March 31, 2011Applicant: Samsung Electronics Co., Ltd.Inventors: Dong-su Jang, In-Chul Jeong
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Patent number: 7852703Abstract: A semiconductor memory device and a layout structure of sub-word line control signal generators. The sub-word line control signal generators are configured to supply a sub-word line control signal of a predefined voltage level to a sub-word line driver to enable a sub-word line of a memory cell array. At least two sub-word line control signal generators are disposed, respectively, at edge areas of the memory cell array, to directly supply the sub-word line control signal to one selected sub-word line driver, thereby reducing the power consumption, including for example, VPP voltage. Embodiments of the present invention also reduce the number of VPP power lines, thereby lessening a noise disturbance.Type: GrantFiled: July 22, 2008Date of Patent: December 14, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Su Jang, In-Chul Jeong
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Publication number: 20100246295Abstract: A semiconductor memory device comprises a memory cell configured to output data to a pair of bitlines, a variable delay circuit configured to receive a sense amplifier enable signal, adjust a delay of the sense amplifier enable signal by changing a slope of a delay based on a variable external power supply voltage, and output a delayed sense amplifier enable signal, and a bitline sense amplifier configured to amplify a voltage difference between the pair of bitlines in response to the delayed sense amplifier enable signal and output the amplified voltage difference to a pair of input/output lines.Type: ApplicationFiled: March 25, 2010Publication date: September 30, 2010Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Su JANG, Yong-Ho CHO
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Publication number: 20090034313Abstract: A semiconductor memory device and a layout structure of sub-word line control signal generators. The sub-word line control signal generators are configured to supply a sub-word line control signal of a predefined voltage level to a sub-word line driver to enable a sub-word line of a memory cell array. At least two sub-word line control signal generators are disposed, respectively, at edge areas of the memory cell array, to directly supply the sub-word line control signal to one selected sub-word line driver, thereby reducing the power consumption, including for example, VPP voltage. Embodiments of the present invention also reduce the number of VPP power lines, thereby lessening a noise disturbance.Type: ApplicationFiled: July 22, 2008Publication date: February 5, 2009Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Su JANG, In-Chul JEONG
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Publication number: 20050218788Abstract: An electron emission display includes: a rear plate including an electron emission device; a front plate spaced from the rear plate and including a fluorescent layer adapted to emit light in response to electrons emitted by the electron emission device colliding with the fluorescent layer; and a grid electrode arranged in a space between the rear and front plates and having a grid substrate including an aperture through which electrons emitted by the electron emission device pass and a film of a photo absorbing material arranged on a surface of the grid substrate. With this configuration, light from a fluorescent layer or secondary electrons, which travel towards a rear plate while the electron emission display operates, are absorbed in the blackened film to prevent other fluorescent layers from emitting light, thereby improving brightness and color purity of the electron emission display.Type: ApplicationFiled: March 22, 2005Publication date: October 6, 2005Inventors: Dong-Su Jang, Jae-Hoon Lee