Abstract: An automatic transportation control method includes moving, by an automatic guidance vehicle, to a first node which is an initial reference location according to an instruction from an automatic transportation control apparatus; moving, by the automatic guidance vehicle, to a second node which is a stand-by location before entering a production facility from the first node; moving, by the automatic guidance vehicle, to a third node for docking to the production facility from the second node; and receiving, by the automatic guidance vehicle, the changed location coordinate value of the second node from the automatic transportation control apparatus, and traveling based on the changed location coordinate value of the second node when the second node is changed according to a work location change of the production facility.

Abstract: A blood glucose measurement device according to an embodiment of the present invention comprises: a measurement unit that is partially inserted into the body of a subject and generates a blood glucose measurement signal by measuring a blood glucose concentration of the subject; a control unit that generates blood glucose measurement data by converting the blood glucose measurement signal into digital data; and a storage unit that stores the blood glucose measurement data, wherein the control unit stores the preset first verification data in the storage unit, and stores the blood glucose measurement data in the storage unit continuously to the first verification data.

Abstract: A blood glucose measurement device according to an embodiment of the present invention comprises: a measurement unit that is partially inserted into the body of a subject and generates a blood glucose measurement signal by measuring a blood glucose concentration of the subject; a control unit that generates blood glucose measurement data by converting the blood glucose measurement signal into digital data; a storage unit that includes a plurality of storage areas and stores the blood glucose measurement data in the plurality of storage areas; and a communication unit that transmits the blood glucose measurement data stored in at least one of the plurality of storage areas to an external device.

Abstract: Proposed is a method of synthesizing reactor core power distribution using an in-core instrument in a reactor core protection system, that is, a method of synthesizing reactor core power distribution for a reactor core protection system based on an in-core instrument signal using an ordinary kriging method. According to the present disclosure, a power of all fuel assemblies in a reactor core is calculated from powers of fuel assemblies where in-core instruments are located using the ordinary kriging methodology, and a hot-pin power distribution of each fuel assembly is synthesized from the power of all fuel assemblies calculated, whereby there is an effect that more accurate hot-pin axial power distribution, rather than pseudo hot-pin axial power distribution, may be synthesized.

Abstract: A power noise filter and a supply modulator including the same, and a wireless communication device including the power noise filter are provided. The power noise filter includes a band stop filter and a low pass filter. The band stop filter includes an inductor and a first capacitor, which are connected in parallel between first and second nodes. The first node receives a first voltage, which is filtered by the band pass filter to thereby generate a second voltage at the second node. The first low pass filter includes the inductor and a second capacitor, which has one end connected to the second node and an opposite end connected to a ground source.

Abstract: A semiconductor device is provided. The semiconductor device comprises an output terminal from which an output voltage is output, a switching converter configured to control the output voltage on the basis of a first reference voltage, a load capacitor configured to be charged with a voltage corresponding to the output voltage, a linear amplifier connected to one end of an alternating current (AC) coupling capacitor and configured to control a voltage of the AC coupling capacitor on the basis of a second reference voltage, and a switching circuit configured to control a charging speed of the load capacitor and control a connection between the output terminal and one end and another end of the AC coupling capacitor.

Abstract: An antenna-integrated high-frequency semiconductor package, including a substrate including a recess concave on a first surface and a first through-hole penetrating from the first surface to a second surface, a ground layer configured to cover the first surface of the substrate and the recess, a semiconductor chip mounted on the ground layer of the recess, an insulating layer configured to entirely cover the substrate, the ground layer, and the semiconductor chip, and a conductive layer formed on the insulating layer, the conductive layer including an electrode pattern connected to the semiconductor chip, an antenna formed on a second surface of the insulating layer, and a signal via configured to transmit an electrical signal between the electrode pattern and the antenna through a second through-hole formed in the first through-hole to penetrate from the first surface to the second surface of the insulating layer.

Abstract: The present invention provides a method for manufacturing a high frequency capacitor, including preparing a substrate for formation of the capacitor, forming a dielectric layer at an upper surface of the substrate, forming an upper electrode at an upper surface of the dielectric layer, and removing a portion of a lower surface of the substrate, to expose a lower surface of the dielectric layer, and forming a lower electrode at the lower surface of the dielectric layer. The high frequency capacitor includes a dielectric layer having a uniform surface, a thick upper electrode, and a thick lower electrode and, as such, exhibits high quality factor (Q) even at a high frequency.

Abstract: A substrate analysis apparatus is provided. The substrate analysis includes: an interlayer conveying module configured to transport a first FOUP; an exchange module which is connected to the interlayer conveying module, and configured to transfer a wafer from the first FOUP to a second FOUP; a pre-processing module configured to form a test wafer piece using the wafer inside the second FOUP; an analysis module configured to analyze the test wafer piece; and a transfer rail configured to transport the second FOUP containing the wafer and a tray containing the test wafer piece. The wafer includes a first identifier indicating information corresponding to the wafer, the test wafer piece includes a second identifier indicating information generated by the pre-processing module which corresponds to the test wafer piece, and the analysis module is configured to analyze the first identifier and the second identifier in connection with each other.

Abstract: A new use of estrogen-related receptor ? (ERR?) inhibitor in enhancing cancer treatment and a pharmaceutical composition for inhibiting the resistance of cancer to tyrosine kinase inhibitors and enhancing an anticancer effect are disclosed. The pharmaceutical composition contains an ERR? inhibitor as an active ingredient. The pharmaceutical composition for treating tyrosine kinase inhibitor-resistant advanced cancer. The composition can be administered in combination with tyrosine kinase inhibitor. A method for determining if a cancer is tyrosine kinase-resistant is also disclosed.

Abstract: A quasi-coaxial transmission line, a semiconductor package including the same and a method of manufacturing the same are disclosed. The quasi-coaxial transmission line includes a core, which is formed through an upper surface and a lower surface of a base substrate so as to transmit an electrical signal, and a shield, which is spaced apart from the core and which coaxially surrounds a side surface of the core, at least a portion of the shield being removed so as to form an open portion. The quasi-coaxial transmission line is capable of preventing distortion of an electrical signal at a portion thereof that is connected to an external circuit board and to reduce an area of a semiconductor package including the quasi-coaxial transmission line.

Abstract: A waveguide package and a method for manufacturing the same are disclosed. The waveguide package includes a package structure including a waveguide opened toward one side surface of a substrate, a semiconductor chip mounted on one surface of the package structure and configured to output an electrical signal to the waveguide. Since an interior of the waveguide is filled with air, electrical loss of the waveguide is minimized The cavity is formed by processing the substrate made of photosensitive glass. Accordingly, the waveguide may be accurately formed. An electronic circuit may also be formed at the waveguide package. Accordingly, it may be possible to provide a waveguide package enhanced in degree of integration.

Abstract: A semiconductor device is provided. The semiconductor device comprises an output terminal from which an output voltage is output, a switching converter configured to control the output voltage on the basis of a first reference voltage, a load capacitor configured to be charged with a voltage corresponding to the output voltage, a linear amplifier connected to one end of an alternating current (AC) coupling capacitor and configured to control a voltage of the AC coupling capacitor on the basis of a second reference voltage, and a switching circuit configured to control a charging speed of the load capacitor and control a connection between the output terminal and one end and another end of the AC coupling capacitor.

Abstract: A vertical field effect transistor according to an embodiment of the present invention does not require a spacer and, accordingly, remarkably alleviates the problem that electric charge is scattered at an interface, thereby having excellent electrical characteristics. The vertical field effect transistor includes a substrate, a source electrode positioned on the substrate, an active layer positioned on the source electrode and having vertically grown crystal grains, a drain electrode positioned on the active layer to be spaced by the active layer away from the source electrode, a gate insulating layer positioned on a lateral surface of the active layer, and a gate electrode positioned on the gate insulating layer.

Abstract: A semiconductor package including a semiconductor chip, and a package structure configured to accommodate the semiconductor chip, and a manufacturing method thereof are disclosed. The package structure includes a substrate having one surface and the other surface opposite to the one surface, at least one conductive via extending through one surface and the other surface of the substrate, a wiring layer formed at one surface of the substrate, to transmit an electrical signal, a chip accommodating portion formed through removal of a portion of the substrate from the other surface toward the one surface, and a contact pad connected to the wiring layer and formed to be exposed through the chip accommodating portion. The semiconductor chip is inserted into the chip accommodating portion and is connected to the contact pad. Since the semiconductor chip is mounted after formation of the package structure, yield of the semiconductor package increases.

Abstract: Provided is an equipment front end module (EFEM) including a base configured to communicate with a processor, a tray port on the base, the tray port being configured to load a tray including a stub and a grid holder, a working robot configured to move in a direction on the base, and grasp and convey the stub in the tray and the grid holder in the tray, and a shuttle port on the base, the shuttle port including a first groove configured to fix the stub, and a second groove configured to fix the grid holder, wherein the working robot is further configured to convey the stub to the first groove and convey the grid holder to the second groove.

Abstract: An embodiment of the present disclosure provides a resistive switching memory device including: a lower electrode; an amorphous metal oxide-based first active layer positioned on the lower electrode; an amorphous metal oxide-based second active layer positioned on the first active layer; and an upper electrode positioned on the second active layer, wherein the first active layer and the second active layer are made of the same substance but are different in electrical characteristic, thereby having a voluntary compliance current characteristic and a voluntary current rectification characteristic as a single device having a stable electrical characteristic, a method of manufacturing the resistive switching memory device, and an array including the resistive switching memory device.

Abstract: Provided is a tray including a plate including a first region and a second region, a first groove on the first region of the plate and to which a stub is fixed, and a second groove on the second region of the plate and to which a grid holder is fixed, wherein the stub is configured to store test wafer pieces, and wherein the grid holder is configured to store a test sample.

Abstract: Disclosed is a device and a method for measuring stream water depth in real-time through positioning data filtering to ensure the reliability of the measured water depth data even when the stream water depth measurement data is filtered and applied to a small stream having a small basin area and a steep slope. The device for measuring stream water depth in real-time through positioning data filtering includes: a measuring part for measuring the water depth of a stream to be measured; a positioning data filtering part for filtering the water depth data measured by the measuring means by a local linear regression-based bivariate scatterplot smoothing technique through elastic bandwidth application; and a water depth calculating part for calculating a water depth of the stream to be measured by using the positioning data filtered by the positioning data filtering part, and minimizing the uncertainty of the water depth measurement.

Abstract: A substrate analysis apparatus is provided. The substrate analysis includes: an interlayer conveying module configured to transport a first FOUP; an exchange module which is connected to the interlayer conveying module, and configured to transfer a wafer from the first FOUP to a second FOUP; a pre-processing module configured to form a test wafer piece using the wafer inside the second FOUP; an analysis module configured to analyze the test wafer piece; and a transfer rail configured to transport the second FOUP containing the wafer and a tray containing the test wafer piece. The wafer includes a first identifier indicating information corresponding to the wafer, the test wafer piece includes a second identifier indicating information generated by the pre-processing module which corresponds to the test wafer piece, and the analysis module is configured to analyze the first identifier and the second identifier in connection with each other.