Abstract: The present invention relates to an integrated repeater and an integrated relay system.

Abstract: A display device includes; a panel, a timing controller generating an embedded clock data signal combining image data and a clock signal, and a column driver driving the panel in response to the embedded clock data signal. The data bits within the embedded clock data signal are communicated at one of three voltage levels in a three-level signaling scheme, and the timing controller determines one of the three voltage levels for a current data bit (DIN[n]) within the embedded clock data signal in relation to a voltage level of a previous data bit (DIN[n?1]) within the embedded clock data signal.

Abstract: A driver may include a plurality of data output units and/or a multi-phase clock generator. The plurality of data output units may be configured to output data based on a plurality of clock signals. The multi-phase clock generator may be configured to receive a master clock signal to generate the plurality of clock signals having different phases in a period of the master clock signal and/or to provide the clock signals to the data output units. A number of the clock signals may correspond to a number of the data output units.

Abstract: A network switch control digital video recorder (DVR) is provided. The network switch control DVR includes a network switch module configured to include a plurality of ports via which data is input to or output from at least one camera, a network storage, an external computer, and a DVR module and to multiplex data input or output via the plurality of ports; and the DVR module configured to control the input or output of data to or from the network switch module by monitoring a state of the input or output of data via the plurality of ports.

Abstract: A duty cycle correction circuit apparatus includes a flip-flop, a feedback unit connected between an input node and an output node of the flip-flop to invert an output signal of the flip-flop and to output the inverted signal as an output signal of the feedback unit, and a selection unit to select and output one of a first clock signal and a second clock signal to the flip-flop in response to the output signal of the feedback unit, wherein the first clock signal has a half-period phase difference with respect to the second clock signal. Using clock signals with a half-period phase difference therebetween and a simple digital circuit, the duty cycle correction circuit can correct a duty ratio to 50:50 regardless of an initial condition.

Abstract: A level shifting circuit includes a level shifting unit and an output buffer unit. The level shifting unit generates first and second output signals responsive to first and second input signals. The first and second input signals range between first and second voltage levels, and the first and second input signals are a first differential pair. The first and second output signals range between the first voltage level and a third voltage level greater than the second voltage level, and the first and second output signals are a second differential pair. The output buffer unit inverts the first and second output signals to provide third and fourth output signals, respectively. Duty ratios of the first and second output signals are determined based on delay times of the first and second input signals.

Abstract: A duty cycle correction circuit apparatus includes a flip-flop, a feedback unit connected between an input node and an output node of the flip-flop to invert an output signal of the flip-flop and to output the inverted signal as an output signal of the feedback unit, and a selection unit to select and output one of a first clock signal and a second clock signal to the flip-flop in response to the output signal of the feedback unit, wherein the first clock signal has a half-period phase difference with respect to the second clock signal. Using clock signals with a half-period phase difference therebetween and a simple digital circuit, the duty cycle correction circuit can correct a duty ratio to 50:50 regardless of an initial condition.

Abstract: A current drive circuit includes a differential voltage detector configured to detect a voltage level of a drive node and configured to compare the voltage level of the drive node with a voltage level of a reference voltage to generate a comparison signal, a control logic circuit configured to generate a control signal to provide a current to the drive node based on the comparison signal, and a current driver configured to provide the current to the drive node or provide the current from the drive node based on the control signal. The voltage level of the drive node rapidly reaches the voltage level of the reference voltage.

Abstract: A current mode bus interface system includes a host interface device configured to transmit a reference current and a clock current, and to transmit a data current during a first transfer mode, and to receive a reverse direction data current and compare the reverse direction data current with the reference current to generate a reverse direction data voltage during a second transfer mode; and a client interface device configured to receive the reference current and the clock current and compare the reference current with the clock current to generate a clock voltage, to receive the data current and compare the data current with the reference current to generate a data voltage during the first transfer mode, and to transmit the reverse direction data current through a conducting wire over which the data current is received during the second transfer mode.

Abstract: A current mode bus interface system includes a host interface device configured to transmit a reference current and a clock current, and to transmit a data current during a first transfer mode, and to receive a reverse direction data current and compare the reverse direction data current with the reference current to generate a reverse direction data voltage during a second transfer mode; and a client interface device configured to receive the reference current and the clock current and compare the reference current with the clock current to generate a clock voltage, to receive the data current and compare the data current with the reference current to generate a data voltage during the first transfer mode, and to transmit the reverse direction data current through a conducting wire over which the data current is received during the second transfer mode.

Abstract: A display device includes; a panel, a timing controller generating an embedded clock data signal combining image data and a clock signal, and a column driver driving the panel in response to the embedded clock data signal. The data bits within the embedded clock data signal are communicated at one of three voltage levels in a three-level signaling scheme, and the timing controller determines one of the three voltage levels for a current data bit (DIN[n]) within the embedded clock data signal in relation to a voltage level of a previous data bit (DIN[n?1]) within the embedded clock data signal.

Abstract: A reference voltage generator and an integrated circuit including the reference voltage generator. The reference voltage generator includes a band gap reference circuit and a start-up circuit. The band gap reference circuit provides a reference voltage to a load. The start-up circuit increases the provided reference voltage by providing a boosting current to the load based on a difference between the provided reference voltage and a target reference voltage responsive to a start-up signal, thereby reducing a time in which the provided reference voltage reaches the target reference voltage. Therefore, the reference voltage generator is configured to provide a target reference voltage within a predetermined time.

Abstract: A driver may include a plurality of data output units and/or a multi-phase clock generator. The plurality of data output units may be configured to output data based on a plurality of clock signals. The multi-phase clock generator may be configured to receive a master clock signal to generate the plurality of clock signals having different phases in a period of the master clock signal and/or to provide the clock signals to the data output units. A number of the clock signals may correspond to a number of the data output units.

Abstract: A low voltage data transmitting circuit (LVDTC) may be connected to a first transmission line that transmits a first voltage signal to a receiver and a second transmission line that transmits a second voltage signal to the receiver. The LVDTC includes a first resistor coupled to the first transmission line, a second resistor coupled to the second transmission line, and a control unit coupled to the first transmission line and the second transmission line, the control unit being configured to control voltage levels of the first and second voltage signals such that the voltage levels of the first and second voltage signals are higher than a ground voltage level of the receiver, wherein the first and second voltage signals may constitute a differential pair.

Abstract: A level shifting circuit includes a level shifting unit and an output buffer unit. The level shifting unit generates first and second output signals responsive to first and second input signals. The first and second input signals range between first and second voltage levels, and the first and second input signals are a first differential pair. The first and second output signals range between the first voltage level and a third voltage level greater than the second voltage level, and the first and second output signals are a second differential pair. The output buffer unit inverts the first and second output signals to provide third and fourth output signals, respectively. Duty ratios of the first and second output signals are determined based on delay times of the first and second input signals.

Abstract: A current driver circuit includes a pull-down switch unit that is coupled between a node and a first reference potential and is operative to switch between an on-state and an off-state responsive to an input signal. A pull-up switch unit is coupled between the node and a second reference potential and is operative to switch between an on-state and an off-state, complementary to the pull-down switch unit. A turn-on speed of the pull-up switch unit is slower than that of the pull-down switch unit, and a turn-off speed of the pull-up switch unit is faster than that of the pull-down switch unit.

Abstract: A current mode bus interface system includes a host interface device configured to transmit a reference current and a clock current, and to transmit a data current during a first transfer mode, and to receive a reverse direction data current and compare the reverse direction data current with the reference current to generate a reverse direction data voltage during a second transfer mode; and a client interface device configured to receive the reference current and the clock current and compare the reference current with the clock current to generate a clock voltage, to receive the data current and compare the data current with the reference current to generate a data voltage during the first transfer mode, and to transmit the reverse direction data current through a conducting wire over which the data current is received during the second transfer mode.

Abstract: A method for sampling reverse data and a reverse data sampling circuit for performing the same are provided. The reverse data sampling method of a host interface device includes generating a multi-phase clock; sampling clocks corresponding to respective phases of the multi-phase clock at a transition of a reverse data signal to generate clock sampling signals; sampling the reverse data signal at a transition of the clocks corresponding to the respective phases of the multi-phase clock to generate data sampling signals; selecting a sampling clock from the clocks corresponding to the respective phases of the multi-phase clock by using the clock sampling signals and the data sampling signals; and sampling reverse data at a transition of the sampling clock.

Abstract: A current drive circuit includes a differential voltage detector configured to detect a voltage level of a drive node and configured to compare the voltage level of the drive node with a voltage level of a reference voltage to generate a comparison signal, a control logic circuit configured to generate a control signal to provide a current to the drive node based on the comparison signal, and a current driver configured to provide the current to the drive node or provide the current from the drive node based on the control signal. The voltage level of the drive node rapidly reaches the voltage level of the reference voltage.

Abstract: A current driver circuit includes a pull-down switch unit that is coupled between a node and a first reference potential and is operative to switch between an on-state and an off-state responsive to an input signal. A pull-up switch unit is coupled between the node and a second reference potential and is operative to switch between an on-state and an off-state, complementary to the pull-down switch unit. A turn-on speed of the pull-up switch unit is slower than that of the pull-down switch unit, and a turn-off speed of the pull-up switch unit is faster than that of the pull-down switch unit.