Abstract: Disclosed herein is an inspection robot system for the customs inspection of container-loaded cargo. The inspection robot system includes: an attachment-type mobile robot configured to drive in the state of being attached to the top surface of a container; and a flexible robot system configured to interface with the attachment-type mobile robot, to selectively accommodate and extend a flexible robot having multiple degrees of freedom, and to perform inspection on cargo.

Abstract: An electronic device including a processor and a sensor may be provided. The processor obtains a first degree of degradation of a first core based on a first parameter value associated with a lifetime of the first core and a first operating level associated with an operation of the first core. The processor obtains a second degree of degradation of a second core based on a second parameter value associated with a lifetime of the second core and a second operating level associated with an operation of the second core. The processor schedules a task of the first core and the second core based on the first degree of degradation and the second degree of degradation. The sensor provides the first parameter value and the first operating level to the first core and the second parameter value and the second operating level to the second core.

Abstract: An apparatus includes a memory configured to store data, and a processor. The processor configured to determine whether an access to the data is a local memory access; determine, based on a result of the determination of whether the access to the data is the local memory access, whether a page fault of the access occurred; determine, based on a result of the determination of whether the page fault occurred, whether the access is a remote access outside a socket; and perform, based on a result of the determination of whether the access is the remote access, the access to the data by copying the data onto a local memory.

Abstract: Embodiments may relate to processing an access request to a memory. The access request to the memory may be based on a first virtual memory address. If a first physical memory address corresponding to the first virtual memory address is determined to be not acquired (e.g., based on a page table), it may be determined whether the first virtual memory address is a valid address. If the first virtual memory address is a valid address, a target virtual memory space or a target physical memory space for the access request may be allocated based on a free memory pool for the target kernel. The free memory pool may include currently allocated virtual and/or physical memory. The access request may be processed based on the allocated target virtual memory space or target physical memory space.

Abstract: An electronic device including a processor and a sensor may be provided. The processor obtains a first degree of degradation of a first core based on a first parameter value associated with a lifetime of the first core and a first operating level associated with an operation of the first core. The processor obtains a second degree of degradation of a second core based on a second parameter value associated with a lifetime of the second core and a second operating level associated with an operation of the second core. The processor schedules a task of the first core and the second core based on the first degree of degradation and the second degree of degradation. The sensor provides the first parameter value and the first operating level to the first core and the second parameter value and the second operating level to the second core.

Abstract: An electronic device including a processor and a sensor may be provided. The processor obtains a first degree of degradation of a first core based on a first parameter value associated with a lifetime of the first core and a first operating level associated with an operation of the first core. The processor obtains a second degree of degradation of a second core based on a second parameter value associated with a lifetime of the second core and a second operating level associated with an operation of the second core. The processor schedules a task of the first core and the second core based on the first degree of degradation and the second degree of degradation. The sensor provides the first parameter value and the first operating level to the first core and the second parameter value and the second operating level to the second core.

Abstract: A processor-implemented method performed by an electronic apparatus includes determining a second voltage obtained by reducing a first voltage by a voltage having a preset magnitude, controlling a target semiconductor chip such that the target semiconductor chip performs a preset target task based on the second voltage, determining whether a result of the target task is the same as a reference result preset for the target task, and determining the first voltage as being a low supply voltage of the target semiconductor chip, in response to the result differing from the reference result.

Abstract: An electronic device including a processor and a sensor may be provided. The processor obtains a first degree of degradation of a first core based on a first parameter value associated with a lifetime of the first core and a first operating level associated with an operation of the first core. The processor obtains a second degree of degradation of a second core based on a second parameter value associated with a lifetime of the second core and a second operating level associated with an operation of the second core. The processor schedules a task of the first core and the second core based on the first degree of degradation and the second degree of degradation. The sensor provides the first parameter value and the first operating level to the first core and the second parameter value and the second operating level to the second core.