Abstract: A silicon interposer includes a plurality of patterned metal layers formed on a silicon wafer portion and a plurality of through-silicon vias extending through the silicon wafer portion. The through-silicon vias have an interdiffusion conductive element.

Abstract: A method for testing TSVs is provided. A plurality of TSVs is formed in a semiconductor substrate. Wiring layers and a first contact array are formed on the front-side of the substrate. The wiring layers couple each of the TSVs to a respective contact of the first contact array. Conductive adhesive is deposited over the first contact array. The conductive adhesive electrically couples contacts of the first contact array. A carrier is bonded to the front-side of the substrate with the conductive adhesive. After bonding the carrier to the substrate, the back-side of the substrate is thinned to expose each of the TSVs on the back-side of the substrate. A second contact array is formed, having a contact coupled to each respective TSV. Conductivity and connections of the TSVs, wiring layers, and contacts are tested by testing for conductivity between contacts of the second contact array.

Abstract: A silicon substrate has a conductive via extending from a first surface of the silicon substrate through the silicon substrate to a second surface of the silicon substrate. A dielectric via extends from the second surface of the silicon substrate toward the first surface of the silicon substrate.

Abstract: An integrated circuit package assembly includes a substrate, a semiconductor die having opposing first and second surfaces, and a head-spreader. The semiconductor die is mounted on the substrate with the first surface facing the substrate. The heat-spreader includes a central region thermally coupled to the second surface of the semiconductor die, a flange region mounted on the substrate, and a side wall region between the central and flange regions. A cavity is formed between the heat-spreader, the substrate, and the semiconductor die. The heat-spreader has at least one vent extending from the cavity through the heat-spreader.

Abstract: A silicon substrate has a conductive via extending from a first surface of the silicon substrate through the silicon substrate to a second surface of the silicon substrate. A dielectric via extends from the second surface of the silicon substrate toward the first surface of the silicon substrate.

Abstract: A microelectronic assembly and a method of forming the assembly. The microelectronic assembly includes a package having a package substrate having a die side and a carrier side, and substrate lands on the carrier side thereof; a microelectronic die mounted on the package substrate at the die side thereof; and an array of first level interconnects electrically coupling the die to the package substrate. The assembly further includes a carrier having a substrate side, the package being mounted on the carrier at the substrate side thereof; and an array of second level interconnects electrically coupling the package to the carrier, each of the second level interconnects including a solder joint connecting the substrate lands to the carrier lands, and a crack arrester element at least partially encompassed within the solder joint.

Abstract: A microelectronic assembly and a method of forming the assembly. The microelectronic assembly includes a package having a package substrate having a die side and a carrier side, and substrate lands on the carrier side thereof; a microelectronic die mounted on the package substrate at the die side thereof; and an array of first level interconnects electrically coupling the die to the package substrate. The assembly further includes a carrier having a substrate side, the package being mounted on the carrier at the substrate side thereof; and an array of second level interconnects electrically coupling the package to the carrier, each of the second level interconnects including a solder joint connecting the substrate lands to the carrier lands, and a crack arrester element at least partially encompassed within the solder joint.

Abstract: A hole capacitor is formed which has a first electrode with a plurality of holes and projections. Another electrode is matched with the first electrode and separated from the first electrode by a dielectric layer. A method for making the hole capacitor includes the steps of: depositing a nitride layer and a lower oxide layer, and forming a buried contact hole, after forming an MOS transistor upon a semiconductor substrate. Thereafter depositing an in-situ doped non-single crystalline silicon layer, an undoped non-single crystalline silicon layer, and a hemispherical polysilicon layer in all in sequence with a thickness of 1500 .ANG. or over. An upper oxide film is deposited, and then, carrying out an etch-back on the upper oxide film so that the hemispherical polysilicon domes are exposed.

Abstract: Methods of hyperfine patterning and manufacturing semiconductor devices. Steps in accordance with the present invention include coating a hemisphere particle layer having hills and valleys on a layer to be etched, the hemisphere particle layer having an etch selectivity higher than that of the first layer, filling the valleys of the hemisphere particle layer with a second layer having an etch selectivity higher than that of the hemisphere particle layer, and etching back the hills of the hemisphere particle layer to expose the first layer by using the second layer as a mask, and etching the first layer. By virtue of the hemisphere particle layer having alternating hills and valleys, it is possible to accomplish a hyperfine patterning of about 0.1 .mu.m. Since the mean size and the density of hills and valleys of the hemisphere layer can be controlled, the pattern size also can be controlled.

Abstract: A method for making a hole capacitor for DRAM cell includes the steps of: depositing a nitride layer and a lower oxide layer, and forming a buried contact hole, after forming a MOS transistor upon a semiconductor substrate. Thereafter depositing an in-situ doped non-crystalline silicon layer, an undoped non-crystalline silicon layer, and a hemispherical polysilicon layer in all in sequence with a thickness of 1500 .ANG. or over. An upper oxide film is deposited, and then, carrying out an etch-back on the upper oxide film so that the hemispherical polysilicon domes are exposed. Etching the polysilicon layers using the remained portions of the upper oxide film remaining on the valleys of the hemispherical polysilicon as a mask, in order to form a plurality of holes perforated from the domes to the insulating layer located under the layers. The upper oxide film is removed through an etch process.

Abstract: Methods of hyperfine patterning and manufacturing semiconductor devices. Steps in accordance with the present invention include coating a hemisphere particle layer having hills and valleys on a layer to be etched, the hemisphere particle layer having an etch selectivity higher than that of the first layer, filling the valleys of the hemisphere particle layer with a second layer having an etch selectivity higher than that of the hemisphere particle layer, and etching back the hills of the hemisphere particle layer to expose the first layer by using the second layer as a mask, and etching the first layer. By virtue of the hemisphere particle layer having alternating hills and valleys, it is possible to accomplish a hyperfine patterning of about 0.1 .mu.m. Since the mean size and the density of hills and valleys of the hemisphere layer can be controlled, the pattern size also can be controlled.

Abstract: A DNA fragment containing a promoter region for human polypeptide chain elongation factor-1.alpha., its base sequence and expression plasmids containing the DNA fragment having high applicability to a wide range of host cells with high expression capacity. These expression plasmids can be maintained stably for at least one month in mammalian host cells. Such features of the expression plasmids may render possible the efficient production of various kinds of useful physiologically active substances for a long period using wide range of mammalian cells as the host.

Abstract: A method and apparatus for removing fluid and cooling the wad of textured yarn on the barrier screen of a moving cavity texturing jet by deflecting the hot fluid (such as steam) away from the underside of the screen with rotating turbine blades and by drawing ambient air across the screen with a vacuum line under the screen has been discovered.

Abstract: Apparatus and method are disclosed to prevent melted yarn when stopped in a high temperature texturing jet device utilizing high temperature fluid such as steam. The device of this invention is attached to the prior art texturing jet device. The attachment comprises a sleeve around the yarn ejector. The sleeve has at least two orifices communicating with a conduit for high pressure fluid having a valve actuated by a sensor to detect yarn stoppage. The high pressure fluid, such as air, blows the yarn plug and yarn from the texturing jet device. The method comprises sensing yarn stoppage with a sensor and actuating the valve in the high pressure fluid conduit communicating with at least two orifices in the sleeve surrounding at least the down stream portion of the injector and blowing any yarn in the texturing chamber out of the chamber with high pressure fluid.