Patents by Inventor Dong-Won Park
Dong-Won Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230318654Abstract: A transceiver device includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. The transmitter encodes an original payload to generate a first payload in the second mode, and transmits a clock training pattern and the first payload through the first line and the second line. The receiver decodes the first payload and outputs reception data corresponding to the original payload in the second mode.Type: ApplicationFiled: October 26, 2022Publication date: October 5, 2023Inventors: Jun Yong SONG, Hyun Su KIM, Dong Won PARK, Jong Man BAE
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Publication number: 20230306893Abstract: A transceiver includes a transmitter and a receiver connected to each other by a first line and a second line. The transmitter transmits signals each having a first voltage range to the first line and the second line in a first mode, and signals each having a second voltage range less than the first voltage range to the first line and the second line in a second mode. The receiver includes a low-power driver which receives signals through the first line and the second line in an operating state of the first mode, and stops an operation thereof in the second mode, and a high-speed driver which receives signals through the first line and the second line in the second mode, and stops an operation thereof in the first mode.Type: ApplicationFiled: October 26, 2022Publication date: September 28, 2023Inventors: Hyun Su Kim, Dong Won Park, Jun Yong Song, Tae Young Jin
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Publication number: 20230260479Abstract: An electronic device includes a host processor including a data transmitter, a driving driver, and a display panel. The data transmitter includes a phase locked loop that generates a first clock and a second clock, a clock block that receives the first clock, a plurality of data blocks that receives the second clock, a first buffer connected between the phase locked loop and the clock block, and a plurality of second buffers respectively connected between the phase locked loop and the plurality of data blocks, and the first buffer and each of the plurality of second buffers may be activated or deactivated depending on an interface mode.Type: ApplicationFiled: December 14, 2022Publication date: August 17, 2023Inventors: JONGMAN BAE, JUNDAL KIM, HYUNSU KIM, DONG-WON PARK, JUNYONG SONG, TAEYOUNG JIN
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Publication number: 20230230526Abstract: A data transceiver system includes an encoder which generates first encoded data by performing a logical operation based on a random number and image data, and generates second encoded data by inverting the first encoded data every N bits, where N is a positive integer greater than or equal to 2, and a decoder which restores the first encoded data by decoding the second encoded data, and restores the image data by decoding the first encoded data.Type: ApplicationFiled: January 13, 2023Publication date: July 20, 2023Inventors: JUNDAL KIM, HYUNSU KIM, KYUNGYOUL MIN, DONG-WON PARK, CHAEHEE PARK, JONGMAN BAE
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Publication number: 20230215351Abstract: A light emitting display device can include a display panel configured to display an image, a driver configured to drive the display panel, and a power supply configured to supply a high-level voltage to a first power line of the display panel. Also, the power supply includes a voltage controller configured to receive, from the driver, a vertical synchronization signal and current amount information of the high-level voltage for driving of the display panel, and boost the high-level voltage to be supplied to the display panel during a vertical blank period, based on the vertical synchronization signal and the current amount information of the high-level voltage.Type: ApplicationFiled: October 31, 2022Publication date: July 6, 2023Applicant: LG Display Co., Ltd.Inventors: Jung Jae KIM, Dong Won PARK, Yong Chul KWON
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Publication number: 20230206885Abstract: A device for controlling a data interface of a display apparatus, can include a timing controller to encode one data transfer packet including image data according to a pixel clock to output the one data transfer packet to an interface line, and a source driver to decode the one data transfer packet to recover the image data. Also, the image data includes first image data of a first color and second image data of a second color between a first delimiter signal having a first logic value and a second delimiter signal having a second logic value, a most significant bit of the first image data is closer to the first delimiter signal than a least significant bit of the first image data, and a most significant bit of the second image data is closer to the second delimiter signal than a least significant bit of the second image.Type: ApplicationFiled: October 26, 2022Publication date: June 29, 2023Applicant: LG Display Co., Ltd.Inventors: Yong Chul KWON, Dong Won PARK
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Publication number: 20230196982Abstract: A display panel includes a plurality of pixels. Each of the pixels includes a first transistor having a gate electrode connected to a first node and a first electrode to which a high level driving voltage is applied, a light emitting device having an anode electrode connected to a second electrode of the first transistor and a cathode electrode to which a low level driving voltage is applied, a second transistor applying a fixing voltage to the first node based on a first gate signal, a third transistor applying a data voltage to a second node based on the first gate signal, a fourth transistor connecting the second node to an input terminal for the low level driving voltage based on a second gate signal having a phase opposite to a phase of the first gate signal, and a capacitor between the first node and the second node.Type: ApplicationFiled: October 6, 2022Publication date: June 22, 2023Applicant: LG Display Co., Ltd.Inventors: Joon Hee LEE, Jong Min PARK, Nam Kon KO, Dong Won PARK, Yong Chul KWON
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Patent number: 11677536Abstract: A transceiver includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. In transmitting a (1-1)-th payload to the receiver, the transmitter is sequentially driven in the first mode, the second mode, and the first mode, and transmits a first clock training pattern and the (1-1)-th payload in the second mode. The receiver includes a clock data recovery circuit generating a first clock signal corresponding to the received first clock training pattern and a register storing first frequency information and first phase information of the first clock training pattern.Type: GrantFiled: January 13, 2022Date of Patent: June 13, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Hyun Su Kim, Dong Won Park, Jun Dal Kim, Kyung Youl Min, Jong Man Bae, Jun Yong Song, Tae Young Jin
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Publication number: 20230170997Abstract: A transceiver includes a transmitter and a receiver which are connected to each other through a first line and a second line. The transmitter transmits a first clock training pattern to the receiver in a first period, transmits a second clock training pattern and a first first payload to the receiver in a second period, and transmits a third clock training pattern and a second first payload to the receiver in a third period. The first clock training pattern, the second clock training pattern, and the third clock training pattern are variable based on a plurality of driving modes.Type: ApplicationFiled: October 4, 2022Publication date: June 1, 2023Inventors: Dong Won PARK, Jun Dal KIM, Hyun Su KIM, Jong Man BAE, Jun Yong SONG, Tae Young JIN
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Patent number: 11657763Abstract: A display device includes a display panel displaying an image, a scan driver configured to apply scan signals to the display panel, and a power supply configured to apply a gate high voltage and a gate low voltage to the scan driver. The scan driver discharges the display panel based on a second gate high voltage lower than the gate high voltage during a discharging operation of the display panel.Type: GrantFiled: September 30, 2021Date of Patent: May 23, 2023Assignee: LG Display Co., Ltd.Inventors: Dong Ju Kim, Soon Dong Cho, Jun O Hur, Dong Won Park, Won Yong Jang
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Patent number: 11645738Abstract: An image deblurring method and an apparatus performing the same are disclosed. The image deblurring method according to an example embodiment includes receiving a blurred image, and deblurring of outputting a sharp original image based on the blurred image. The deblurring includes obtaining a second image having the same scale as that of a first image by inputting the first image to a neural network, obtaining a third image having the same scale as that of the first image by concatenating the first image and the second image, and obtaining a fourth image having the same scale as that of the first image by inputting the third image to the neural network.Type: GrantFiled: November 12, 2020Date of Patent: May 9, 2023Assignee: UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)Inventors: Se Young Chun, Dong Won Park, Dong Un Kang
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Patent number: 11630355Abstract: A display device is disclosed. The display device includes a display panel configured to display an image, and a printed circuit board electrically connected to the display panel and disposed at a back surface of the display panel. The printed circuit board includes an insulating layer, a first metal layer disposed at one surface of the insulating layer, pads including a first pad disposed on the first metal layer while being disposed inside a mounting area where an integrated circuit is mounted, and second pads disposed around the first pad, and a groove provided to extend from an inside of the mounting area to an outside of the mounting area.Type: GrantFiled: December 3, 2020Date of Patent: April 18, 2023Assignee: LG Display Co., Ltd.Inventors: Jeong-Kyu Lee, Dong-Won Park, Min-Gyu Park, Nam-Kon Ko
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Patent number: 11558080Abstract: A transceiver device includes a transmitter and a receiver connected through first and second lines. A first frame period includes an active period for transmitting a first payload and a vertical blank period including a frequency hopping period. The transmitter transmits, to the first and second lines, signals having a first voltage range in a first mode and signals having a second voltage range in a second mode. The transmitter generates a first horizontal synchronization signal in the second mode except for the frequency hopping period, encodes the first horizontal synchronization signal to horizontal synchronization data, and generates a second horizontal synchronization signal in the first mode in the frequency hopping period. The transmitter adds a first clock training pattern to the horizontal synchronization data except for the frequency hopping period, and adds a second clock training pattern to first horizontal synchronization data after the frequency hopping period.Type: GrantFiled: January 14, 2022Date of Patent: January 17, 2023Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Tae Young Jin, Dong Won Park, Jun Dal Kim, Hyun Su Kim, Kyung Youl Min, Jong Man Bae, Jun Yong Song
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Publication number: 20230011169Abstract: An assistive system according to an embodiment of the present disclosure includes a cradle module including a holder body on which a user terminal is to be placed and a drive unit configured to drive the holder body, the cradle module configured to output a terminal connection signal when the user terminal is placed on the holder body, and an assistant server configured to receive the terminal connection signal from the cradle module and execute an assistive service, the assistant server configured to control the drive unit by a preset drive pattern through a drive control signal when executing the assistive service. It is possible to easily and conveniently identify a plurality of assistive services outputted according to each situation by controlling a cradle module through a drive pattern corresponding to an assistive service while outputting a voice corresponding to the assistive service when executing the assistive service.Type: ApplicationFiled: November 3, 2020Publication date: January 12, 2023Inventors: Seung-Yub KOO, Seong-Taek HWANG, Bo-Kyu WON, Dong-Won PARK, Seon-Ho YOO, Sin-Jong NA, Dong-Su SHIN, Sung-Eon KONG
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Publication number: 20230005435Abstract: A display device includes a display panel including pixels, and data lines and gate lines connected to the pixels, a timing controller configured to output source driving bit information and gate driving bit information through an intra-interface signal, a source driver configured to generate data driving signal based on the source driving bit information and to supply the data driving signal to the data lines, and a gate driver configured to generate a gate driving signal based on the gate driving bit information and to supply the gate driving signal to the gate lines, wherein the intra-interface signal is configured with predetermined data transmission units and includes both the source driving bit information and the gate driving bit information every 1 data transmission unit.Type: ApplicationFiled: September 13, 2022Publication date: January 5, 2023Applicant: LG DISPLAY CO., LTD.Inventors: Soon-Dong CHO, Jung-Jae KIM, Min-Gyu PARK, Jae-Won HAN, Dong-Won PARK
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Publication number: 20220416841Abstract: A transceiver device includes a transmitter and a receiver connected through first and second lines. A first frame period includes an active period for transmitting a first payload and a vertical blank period including a frequency hopping period. The transmitter transmits, to the first and second lines, signals having a first voltage range in a first mode and signals having a second voltage range in a second mode. The transmitter generates a first horizontal synchronization signal in the second mode except for the frequency hopping period, encodes the first horizontal synchronization signal to horizontal synchronization data, and generates a second horizontal synchronization signal in the first mode in the frequency hopping period. The transmitter adds a first clock training pattern to the horizontal synchronization data except for the frequency hopping period, and adds a second clock training pattern to first horizontal synchronization data after the frequency hopping period.Type: ApplicationFiled: January 14, 2022Publication date: December 29, 2022Inventors: Tae Young JIN, Dong Won PARK, Jun Dal KIM, Hyun Su KIM, Kyung Youl MIN, Jong Man BAE, Jun Yong SONG
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Publication number: 20220397932Abstract: A data receiver, which communicates with a data transmitter through a plurality of lanes, includes: a first reception unit which receives first data through a first lane; a second reception unit which receives second data through a second lane; and a detector which compares the first data and the second data to detect a skew between the first lane and the second lane. The first reception unit includes a first clock data recovery unit which recovers a first clock and first payload data from the first data. The first reception unit controls a loop speed of the first clock data recovery unit based on a skew level of the skew.Type: ApplicationFiled: March 25, 2022Publication date: December 15, 2022Inventors: Jun Dal KIM, Dong Won PARK, Hyun Su KIM, Kyung Youl MIN, Jong Man BAE, Jun Yong SONG, Tae Young JIN
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Publication number: 20220397931Abstract: A transceiver includes a transmitter and a receiver connected to each other by a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range smaller than the first voltage range to the first line and the second line in a second mode. The transmitter encodes an original payload in the second mode to generate a first payload, and transmits the clock training pattern and the first payload through the first line and the second line.Type: ApplicationFiled: January 12, 2022Publication date: December 15, 2022Inventors: Jun Yong SONG, Jong Man BAE, Jun Dal KIM, Hyun Su KIM, Kyung Youl MIN, Dong Won PARK, Tae Young JIN
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Publication number: 20220399986Abstract: A transceiver includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. In transmitting a (1-1)-th payload to the receiver, the transmitter is sequentially driven in the first mode, the second mode, and the first mode, and transmits a first clock training pattern and the (1-1)-th payload in the second mode. The receiver includes a clock data recovery circuit generating a first clock signal corresponding to the received first clock training pattern and a register storing first frequency information and first phase information of the first clock training pattern.Type: ApplicationFiled: January 13, 2022Publication date: December 15, 2022Inventors: Hyun Su KIM, Dong Won PARK, Jun Dal KIM, Kyung Youl MIN, Jong Man BAE, Jun Yong SONG, Tae Young JIN
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Patent number: 11475843Abstract: A display device includes a display panel including pixels, and data lines and gate lines connected to the pixels, a timing controller configured to output source driving bit information and gate driving bit information through an intra-interface signal, a source driver configured to generate data driving signal based on the source driving bit information and to supply the data driving signal to the data lines, and a gate driver configured to generate a gate driving signal based on the gate driving bit information and to supply the gate driving signal to the gate lines, wherein the intra-interface signal is configured with predetermined data transmission units and includes both the source driving bit information and the gate driving bit information every 1 data transmission unit.Type: GrantFiled: December 16, 2020Date of Patent: October 18, 2022Assignee: LG DISPLAY CO., LTD.Inventors: Soon-Dong Cho, Jung-Jae Kim, Min-Gyu Park, Jae-Won Han, Dong-Won Park