Abstract: The present disclosure provides autotaxin (ATX) inhibitor compounds and compositions including said compounds. The present disclosure also provides methods of using said compounds and compositions for inhibiting ATX. Also provided are methods of preparing said compounds and compositions, and synthetic precursors of said compounds.

Abstract: In a method of manufacturing a cathode active material for a lithium secondary battery, a preliminary lithium metal oxide particle is prepared. The preliminary lithium metal oxide particle is cleaned using a boron compound cleaning solution. A cathode active material for a lithium secondary particle includes a lithium metal oxide particle where a ratio of a B+ peak intensity relative to a sum of peak intensities of Li+, B+ and LiB+ fragments by a TOF-SIMS analysis is in a range from 0.03% to 1.5%.

Abstract: A substrate processing apparatus includes a photoresist coater applying a photoresist film on a substrate, a humidifier increasing an amount of moisture in an ambient to which the photoresist film on the substrate is exposed, and an exposer irradiating the photoresist film exposed to the ambient having the increased amount of moisture with light. The humidifier is disposed between the photoresist coater and the exposer.

Abstract: A magnetically shielded current transformer is provided, which includes a magnetic core module including a core formed in a ring shape by winding plate shape ribbon a plurality of times, a bobbin configured to accommodate the core, and a coil configured to be wound along an outer circumferential surface of the bobbin; a shielding member which is configured to surround an outer circumferential surface and both side surfaces of the magnetic core module, includes through-holes at centers of the both side surfaces, and is formed of iron; and an outer case configured to protect the magnetic core module and the shielding member. Accordingly, a magnetic path is formed by an external magnetic field, which is applied from the outside, via the shielding member and thus the external magnetic field is prevented from being transferred to the magnetic core module, thereby stably blocking influences caused by the external magnetic field.

Abstract: A magnetically shielded current transformer is provided, which includes a magnetic core module including a core formed in a ring shape by winding plate shape ribbon a plurality of times, a bobbin configured to accommodate the core, and a coil configured to be wound along an outer circumferential surface of the bobbin; a shielding member which is configured to surround an outer circumferential surface and both side surfaces of the magnetic core module, includes through-holes at centers of the both side surfaces, and is formed of iron; and an outer case configured to protect the magnetic core module and the shielding member. Accordingly, a magnetic path is formed by an external magnetic field, which is applied from the outside, via the shielding member and thus the external magnetic field is prevented from being transferred to the magnetic core module, thereby stably blocking influences caused by the external magnetic field.

Abstract: An impedance calibration circuit may be provided. The impedance calibration circuit may include an adjusting circuit. The adjusting circuit may be configured to generate a calibration code based on a variation voltage, which may be applied to a calibration node coupled to a calibration pad, and a reference voltage. The adjusting circuit may be configured to apply a voltage, which may be generated according to a control signal generated based on an operational voltage mode in accordance with the calibration code, to the calibration node. The adjusting circuit may include a plurality of leg circuits. At least one of the leg circuits may include a plurality of legs configured to be selectively coupled to the calibration node based on the control signal.

Abstract: An impedance calibration circuit includes a first reference resistor electrically coupled to a calibration pad, a second reference resistor which is coupled to the first reference resistor in parallel and a resistance value of the second reference resistor is varied according to an operation voltage mode, and a calibration circuit electrically coupled to the calibration pad and configured to generate a calibration code according to a resistance value formed by the first reference resistor and the second reference resistor and calibrate an impedance value in the calibration pad according to the calibration code.

Abstract: An impedance calibration circuit may be provided. The impedance calibration circuit may include an adjusting circuit. The adjusting circuit may be configured to generate a calibration code based on a variation voltage, which may be applied to a calibration node coupled to a calibration pad, and a reference voltage. The adjusting circuit may be configured to apply a voltage, which may be generated according to a control signal generated based on an operational voltage mode in accordance with the calibration code, to the calibration node. The adjusting circuit may include a plurality of leg circuits. At least one of the leg circuits may include a plurality of legs configured to be selectively coupled to the calibration node based on the control signal.

Abstract: An impedance calibration circuit includes a first reference resistor electrically coupled to a calibration pad, a second reference resistor which is coupled to the first reference resistor in parallel and a resistance value of the second reference resistor is varied according to an operation voltage mode, and a calibration circuit electrically coupled to the calibration pad and configured to generate a calibration code according to a resistance value formed by the first reference resistor and the second reference resistor and calibrate an impedance value in the calibration pad according to the calibration code.

Abstract: A decoding circuit may include a section information generation unit suitable for generating section information corresponding to a section in which an input signal has a first value, a period information generation unit suitable for generating period information corresponding to a period of the input signal, a reference information generation unit suitable for generating reference information by dividing a value of the period information by a given value, and a comparison unit suitable for determining a logic value of the input signal by comparing the section information with the reference information.

Abstract: A data transmission circuit includes a first data selection unit suitable for alternately outputting data of first and second input lines as first driving data in synchronization with a clock; a data delay unit suitable for generating first and second delay data by delaying the data of the first and second input lines in synchronization with the clock; a second data selection unit suitable for: alternately outputting the data of the first and second input lines as second driving data in synchronization with the clock during a first mode, and alternately outputting inverted first and second delay data, which are inverted from the first and second delay data, as the second driving data in synchronization with the clock during a second mode; a first driving unit suitable for driving an output line in response to the first driving data; and a second driving unit suitable for driving the output line in response to the second driving data.

Abstract: An integrated circuit is provided that includes an equalizing unit suitable for equalizing input data that is successively inputted, a sampling unit suitable for sampling centers and edges of the input data that is equalized by the equalizing unit using two or more multi-phase clocks, and a gain adjustment unit suitable for adjusting a gain of the equalizing unit using the centers of the input data and the edges of the input data that are sampled by the sampling unit.

Abstract: Provided are an amorphous metal core that can minimize a core loss in which amorphous thin plate laminates are mutually combined by coupling protrusions and coupling recesses of assembly plates, an induction device, and a method of making the amorphous metal core. The amorphous metal core includes: a number of amorphous metal unit cores that include an amorphous thin plate laminate and a pair of assembly plates that are respectively laminated on the front and rear surfaces of the amorphous thin plate laminate, and are configured to have an I shape, respectively. The induction device includes: an amorphous metal core including a number of amorphous metal unit cores that are formed of an “I” shape, respectively; and at least one coil that is wound on at least one of the amorphous metal unit cores forming the amorphous metal core.

Abstract: A data transmission circuit includes a first data selection unit suitable for alternately outputting data of first and second input lines as first driving data in synchronization with a clock; a data delay unit suitable for generating first and second delay data by delaying the data of the first and second input lines in synchronization with the clock; a second data selection unit suitable for: alternately outputting the data of the first and second input lines as second driving data in synchronization with the clock during a first mode, and alternately outputting inverted first and second delay data, which are inverted from the first and second delay data, as the second driving data in synchronization with the clock during a second mode; a first driving unit suitable for driving an output line in response to the first driving data; and a second driving unit suitable for driving the output line in response to the second driving data.

Abstract: A decoding circuit may include a section information generation unit suitable for generating section information corresponding to a section in which an input signal has a first value, a period information generation unit suitable for generating period information corresponding to a period of the input signal, a reference information generation unit suitable for generating reference information by dividing a value of the period information by a given value, and a comparison unit suitable for determining a logic value of the input signal by comparing the section information with the reference information.

Abstract: An impedance calibration circuit includes a first calibration voltage driver configured to operate in response to a first enable signal, compare a first calibration voltage signal with a first reference voltage signal, and drive the first calibration voltage signal, a first control code generator configured to operate in response to a second enable signal, compare the first calibration voltage signal with a first target voltage signal, and generate a first control code signal, and a first reference voltage generator configured to generate the first reference voltage signal in response to the first control code signal.

Abstract: Provided are an amorphous metal core that can minimize a core loss in which amorphous thin plate laminates are mutually combined by coupling protrusions and coupling recesses of assembly plates, an induction device, and a method of making the amorphous metal core. The amorphous metal core includes: a number of amorphous metal unit cores that include an amorphous thin plate laminate and a pair of assembly plates that are respectively laminated on the front and rear surfaces of the amorphous thin plate laminate, and are configured to have an I shape, respectively. The induction device includes: an amorphous metal core including a number of amorphous metal unit cores that are formed of an “I” shape, respectively; and at least one coil that is wound on at least one of the amorphous metal unit cores forming the amorphous metal core.

Abstract: A signal transmission circuit includes a first selection driver configured to generate a first drive signal in response to an input signal and a first selection signal and drive a transmission signal in response to the first drive signal, and a second selection driver configured to delay the input signal by a first delay time to generate a first delay signal. The second selection driver generates a second drive signal in response to the first delay signal and a second selection signal, generates a first code signal in response to the input signal and the second selection signal, and drives the transmission signal in response to the second drive signal and the first code signal.

Abstract: A signal transmission circuit includes a first selection driver configured to generate a first drive signal in response to an input signal and a first selection signal and drive a transmission signal in response to the first drive signal, and a second selection driver configured to delay the input signal by a first delay time to generate a first delay signal. The second selection driver generates a second drive signal in response to the first delay signal and a second selection signal, generates a first code signal in response to the input signal and the second selection signal, and drives the transmission signal in response to the second drive signal and the first code signal.

Abstract: An impedance calibration circuit includes a first calibration voltage driver configured to operate in response to a first enable signal, compare a first calibration voltage signal with a first reference voltage signal, and drive the first calibration voltage signal, a first control code generator configured to operate in response to a second enable signal, compare the first calibration voltage signal with a first target voltage signal, and generate a first control code signal, and a first reference voltage generator configured to generate the first reference voltage signal in response to the first control code signal.