Patents by Inventor Dong-yeop Kim
Dong-yeop Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240164084Abstract: A semiconductor device includes: a substrate includes an active area; a first landing pad connected to the active area and disposed on the substrate; a second landing pad connected to the active area, and spaced apart from the first landing pad, wherein the second landing pad is disposed on the substrate; a first lower electrode disposed on the first landing pad and extending in a direction substantially perpendicular to the substrate; a second lower electrode disposed on the second landing pad and extending in the direction substantially perpendicular to the substrate; a dielectric layer extending along the first lower electrode and the second lower electrode; and an upper electrode disposed on the dielectric layer, wherein a first upper surface of the first landing pad is disposed below a second upper surface of the second landing pad with respect to a lower surface of the substrate.Type: ApplicationFiled: August 22, 2023Publication date: May 16, 2024Inventors: Do Keun LEE, Dong Wook KIM, Yang Doo KIM, Sang Wuk PARK, Min Kyu SUH, Geon Yeop LEE, Jung Pyo HONG
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Patent number: 11984559Abstract: A systems and methods for tracking a position of an electrode. The system may include: a notching controller configured to store pitch information of a unit electrode and to acquire electrode coordinate information of the electrode in a roll-to-roll state during a notching process and a cell identification (ID) of the unit electrode; a calculator configured to calculate coordinates of the cell ID from the pitch information and the cell ID; a roll map generator configured to generate a roll map based on the electrode coordinate information transmitted from the notching controller; and a mapping part configured to compare the coordinates of the roll map with the coordinates of the cell ID to derive an electrode position of the electrode during the electrode manufacturing process from which the unit electrode originates.Type: GrantFiled: August 8, 2022Date of Patent: May 14, 2024Assignee: LG ENERGY SOLUTION, LTD.Inventors: Jae Hwan Lee, Jong Seok Park, Dong Yeop Lee, Jun Hyo Su, Ki Deok Han, Byoung Eun Han, Seung Huh, Su Wan Park, Gi Yeong Jeon, Min Su Kim
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Publication number: 20240151524Abstract: An apparatus for generating a roll map of a merge-wound electrode includes a position measurement device configured to acquire coordinate value data for a longitudinal position of an electrode according to an amount of rotation of the rewinder. The apparatus includes an input device configured to input an input signal indicating a start of merge-winding or an end of merge-winding, a seam detector configured to detect a seam, a reference point detector configured to detect a plurality of reference points of the merge-wound electrode, and a roll map generator configured to generate a roll map for simulating the merge-wound electrode moving in a roll-to-roll state based on the input signal of the input device, and to display the longitudinal coordinate values of the electrode, the electrode coordinate values of the seam, and the electrode coordinate values of the plurality of reference points of the merge-wound electrode on the roll map.Type: ApplicationFiled: November 7, 2022Publication date: May 9, 2024Inventors: Dong Yeop LEE, Jong Seok PARK, Jun Hyo SU, Ki Deok HAN, Byoung Eun HAN, Seung HUH, Su Wan PARK, Gi Yeong JEON, Jae Hwan LEE, Min Su KIM
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Publication number: 20240097218Abstract: Methods and systems for executing tracking and monitoring manufacturing data of a battery are disclosed. One method includes: receiving, by a server system, sensing data of the battery from a sensing system; generating, by the server system, mapping data based on the sensing data; generating, by the server system, identification data of the battery based on the sensing data; generating, by the server system, monitoring data of the battery based on the sensing data, the identification data, and the mapping data; and generating, by the server system, display data for displaying a simulated electrode of the battery on a graphical user interface based on the monitoring data of the battery.Type: ApplicationFiled: August 31, 2023Publication date: March 21, 2024Inventors: Min Kyu Sim, Jong Seok Park, Min Su Kim, Jae Hwan Lee, Ki Deok Han, Eun Ji Jo, Su Wan Park, Gi Yeong Jeon, June Hee Kim, Wi Dae Park, Dong Min Seo, Seol Hee Kim, Dong Yeop Lee, Jun Hyo Su, Byoung Eun Han, Seung Huh
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Patent number: 10622029Abstract: A memory module includes a module board including a first and second data vias configured to transmit first and second data, respectively, through first and second data lines arranged adjacent to each other external to the module board, a plurality of layers including the first and second data vias passing therethrough, and a plurality of semiconductor memory devices arranged on at least one outer surface of the module board. The plurality of layers include first and second layers adjacent to each other. The module board includes a first data via wing extending from the first data via toward the second data via and not connected to the second data via in the first layer, and a seventh data via wing extending from the second data via toward the first data via and not connected to the first data via to overlap the first data via wing in the second layer.Type: GrantFiled: July 31, 2018Date of Patent: April 14, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Dong Yeop Kim, Jae Jun Lee
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Patent number: 10536127Abstract: A signal channel includes at least one first signal line positioned in a first signal layer and at least one second signal line positioned in a second signal layer. The first signal layer extends in a first horizontal direction. The second signal layer extends along a second horizontal plane parallel to the first horizontal plane and spaced apart from the first horizontal plane along a vertical direction orthogonal to the first and second horizontal planes. The first signal line includes a first coupling segment and the second signal line includes a second coupling segment. The first coupling segment at least partially overlaps the second coupling segment along the vertical direction. The first and second coupling segments are positioned to form a greater degree of capacitive coupling between the first and second coupling segments than a degree of capacitive coupling formed between other segments of the first and second signal lines.Type: GrantFiled: September 29, 2017Date of Patent: January 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-Yeop Kim, Jae-Jun Lee
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Publication number: 20190259426Abstract: A memory module includes a module board including a first and second data vias configured to transmit first and second data, respectively, through first and second data lines arranged adjacent to each other external to the module board, a plurality of layers including the first and second data vias passing therethrough, and a plurality of semiconductor memory devices arranged on at least one outer surface of the module board. The plurality of layers include first and second layers adjacent to each other. The module board includes a first data via wing extending from the first data via toward the second data via and not connected to the second data via in the first layer, and a seventh data via wing extending from the second data via toward the first data via and not connected to the first data via to overlap the first data via wing in the second layer.Type: ApplicationFiled: July 31, 2018Publication date: August 22, 2019Inventors: DONG YEOP KIM, JAE JUN LEE
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Publication number: 20180166105Abstract: A memory module may include a first memory group and a second memory group; and a first clock signal line and a second clock signal line via which the first clock signal and the second clock signal propagate from the buffer chip to the first memory group and the second memory group, respectively, wherein distances that the first clock signals propagate from a buffer chip to a plurality of memory chips of the first memory group via the first clock signal line are identical to one another and are referred to as a first distance, and distances that the second clock signals propagate from the buffer chip to a plurality of memory chips of the second memory group via the second clock signal line are identical to one another and are referred to as a second distance.Type: ApplicationFiled: August 28, 2017Publication date: June 14, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Il-han CHOI, Jae-jun Lee, Dong-yeop Kim, Kyu-dong Lee, Jeong-hyeon Cho
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Publication number: 20180123548Abstract: A signal channel includes at least one first signal line positioned in a first signal layer and at least one second signal line positioned in a second signal layer. The first signal layer extends in a first horizontal direction. The second signal layer extends along a second horizontal plane parallel to the first horizontal plane and spaced apart from the first horizontal plane along a vertical direction orthogonal to the first and second horizontal planes. The first signal line includes a first coupling segment and the second signal line includes a second coupling segment. The first coupling segment at least partially overlaps the second coupling segment along the vertical direction. The first and second coupling segments are positioned to form a greater degree of capacitive coupling between the first and second coupling segments than a degree of capacitive coupling formed between other segments of the first and second signal lines.Type: ApplicationFiled: September 29, 2017Publication date: May 3, 2018Inventors: DONG-YEOP KIM, Jae-Jun Lee
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Publication number: 20180068312Abstract: An electronic device includes a display, a local wireless communication circuit, a memory, a payment application, and a processor. The memory is configured to store a financial application. The processor is configured to launch the financial application. The processor is also configured to output account information of a user and a graphic user interface (GUI) object associated with the account information on the display. The processor is also configured to launch the payment application in response to selecting the GUI object. The processor is also configured to transmit data of a card linked to the account information to an external device via the local wireless communication circuit.Type: ApplicationFiled: September 7, 2017Publication date: March 8, 2018Inventors: Dong Yeop KIM, Soo Bin PARK, Gun Woo BAE, Myung Hwa JUN, Dong Ho JANG
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Publication number: 20090189624Abstract: An interposer and a probe card assembly for electrical die sorting is provided. The assembly may include probes electrically contacting pads of dies on a substrate, a first wiring unit including a first wire on and electrically contacting the probes, an interposer unit including interposers on the first wiring unit and electrically contacting the first wire, and a second wiring unit including a second wire on the interposer unit and electrically contacting the interposers. At least one interposer includes a conductive member, a first connection member adjacent to a first end of the conductive member so as to electrically connect the conductive member to the first wire, a second connection member adjacent to a second end of the conductive member so as to electrically connect the conductive member to the second wire, and at least one protrusion member on an external surface of the conductive member between the first and second connection members.Type: ApplicationFiled: September 26, 2008Publication date: July 30, 2009Inventors: Se-Jang Oh, Hal-young Lee, Young-soo An, Sang-hoon Lee, Sung-ho Joo, Dong-yeop Kim