Abstract: A z-unit for a three-dimensional graphics system is provided having a read buffer and a write buffer. The read buffer stores read requests and the write buffer stores write requests. The read and write requests correspond to atomic operations for z-buffer manipulations. Upon the receipt of a read request, the address of the read request is compared to each of the addresses of the write requests. If a match occurs then the read buffer is flushed until a first read request with the matched address occurs. The write buffer is then flushed and all the write requests within the write buffer is serviced. The read buffer is again flushed until all the read requests within the read buffer is serviced.

Abstract: A z-unit for a three-dimensional graphics system is provided having a read buffer and a write buffer. The read buffer stores read requests and the write buffer stores write requests. The read and write requests correspond to atomic operations for z-buffer manipulations. Upon the receipt of a read request, the address of the read request is compared to each of the addresses of the write requests. If a match occurs then the read buffer is flushed until a first read request with the matched address occurs. The write buffer is then flushed and all the write requests within the write buffer is serviced. The read buffer is again flushed until all the read requests within the read buffer is serviced.

Abstract: A z-unit for a three-dimensional graphics system is provided having a read buffer and a write buffer. The read buffer stores read requests and the write buffer stores write requests. The read and write requests correspond to atomic operations for z-buffer manipulations. Upon the receipt of a read request, the address of the read request is compared to each of the addresses of the write requests. If a match occurs then the read buffer is flushed until a first read request with the matched address occurs. The write buffer is then flushed and all the write requests within the write buffer is serviced. The read buffer is again flushed until all the read requests within the read buffer is serviced.

Abstract: A lighting evaluation unit in a graphics processing system. The lighting evaluation unit includes a calculation unit having dot product circuitry used in determining specular, diffuse, spot, and attenuation components of a lighting equation in parallel. In one embodiment, the lighting evaluation unit is constructed in a pipeline manner, and includes multi-use circuitry for performing dot product calculations.

Abstract: A token-based buffer system for a geometry pipeline in three-dimensional graphics comprises: a buffer control initialization (BCI) unit, a new token or index module, a geometry control pipeline, a vertex buffer, and a processing engine. The token-based buffer system provides a shared resource environment in which tokens are assigned for blocks of data. Each block of data includes that data necessary for each unit or stage in the geometry pipeline to perform its computation. The use of tokens is advantageous because it optimizes the storage efficiency for storing the blocks of data and ensures the correctness of the data as it is passed between stages.

Abstract: A command parser 308 is coupled to an incoming data stream to insert an end of state token at the end of a group of state data 480 and an end of primitive token at the end of a group of primitive data 484 to create a parsed data stream. The parsed state data stream is transmitted to a state controller 420 which loads state data 480 into shadow stages 412. The state controller 420 validates a shadow stage 412 upon receiving an end of state group token. The parsed primitive data 484 are also transmitted to primitive controllers 424. The primitive controllers 424 prevent primitive data from being transmitted into a processing element 464 responsive to receiving an end of primitive_B token. Upon receiving an end of primitive_E token, the primitive controller 424 ascertains whether the first shadow stage 412 has been validated.

Abstract: A dither unit preferably comprises an offset generator, an adjusted coordinate generator and a dither matrix. The offset generator is coupled to receive information about the relative position of the sub-sample being dithered, and in response generates offset values. The output of the offset generator along with the pixel coordinates are provided to the adjusted coordinate generator which generates adjusted coordinate values used by the dither matrix. The adjusted coordinate values along with a color value are received by the dither matrix, which in response, generates a dithered value for the sub-sample that can be stored back in the over sampling buffer for additional computation.

Abstract: The present invention provides an alpha blending unit that is able to perform alpha blending on sub-samples of a pixel in an efficient manner. The alpha blending unit preferably comprises a plurality of registers for storing a source color, a blending value, and a plurality of destination sub-sample values, multipliers, adders, an accumulator and a divider. The alpha blending unit advantageously sums the destination sub-sample values and then divides them by the number of sub-samples to generate a combined destination color value. This combined destination color value along with the source color and a blending value are then provided to the multipliers, and adders to generate a new destination color value for the pixel.

Abstract: A caching system for increasing the operation concurrency between a cache module and a memory module by comparing received memory block identifiers, which correspond to texels needed for pixel composition, with memory block identifiers corresponding to texels locally stored within the cache module. If the received memory block identifiers match the memory block identifiers corresponding to locally cached texels, the system transmits these texels to a texture filter unit for pixel composition. If the received memory block identifiers do not match memory block identifiers corresponding to the locally cached texels, the system retrieves these texels from the memory module as fast as possible and then updates the cache module with the new texels. A plurality of first in, first out buffers are used to assist a controller module with synchronizing the transmission of the texels from the cache module and the overwriting of the texels received from the memory module into the cache module.

Abstract: A system and method for traversing and rendering a graphic primitive represented in screen space, employing block- and band-oriented traversal algorithms in texture mapping. Improved performance is achieved through burst-mode texture access and texture caching in connection with a texture map subdivided into squares. Block- and band-oriented traversal facilitates minimization of page breaks and texture cache swap-out. Improved determinism is facilitated by obviating the need for pixel sorting algorithms. Improved re-use of retrieved data segments in burst-mode access is facilitated.

Abstract: A system and method for reordering memory references for pixels to improved bandwidth and performance in texture mapping systems and other graphics systems by improving memory locality in conventional page-mode memory systems. Pixel memory references are received from a client graphics engine and placed in a pixel priority heap. The pixel priority heap reorders the pixel memory references so that references requiring a currently open page are, in general, processed before references that require page breaks. Reordered pixel memory references are transmitted to a memory controller for accessing memory.

Abstract: A floating point binary number that is to be converted to a fixed point representation, or a fixed point number to be reduced in precision, is originally located in a source register. A conversion mechanism connects the source register to a destination register. After the conversion the least significant bit of the fixed point representation may deliberately retain an indication of the existence of less significant non-zero bits that were truncated. When such retention is desired it is accomplished by forcing that least significant bit to be a one if the fractional portion of the converted number is zero and there were such truncated non-zero bits of lesser significance. To do this the direction and amount of mantissa shift needed during conversion are inspected to reveal which bit positions in the original floating point number are going to be truncated. An array of two-input AND gates has one AND gate per possible truncated bit.