Abstract: In a level shifter, first and second PMOS transistors are connected in series between first and second power sources for supplying first high level and low level voltages, respectively, and a capacitor is formed between a contact point of the first and second transistors and the second transistor's gate. A third PMOS transistor is diode-connected and connected between the first and second transistors' gates. When a second low level voltage is input to the first transistor's gate, a second high level voltage is output to the contact point according to an on resistance ratio of the first and second transistors. When a first high level voltage is input to the first transistor's gate, the second transistor is bootstrapped according to the voltage charged to the capacitor so that a first low level voltage is substantially output to the contact point.

Abstract: A pixel circuit of an organic EL display includes a driving transistor for transmitting a driving current to an organic EL element. A first capacitor is connected between a gate and a source of the driving transistor, and a second capacitor is connected between the gate thereof and a boosting scan line. A voltage corresponding to a data current from a data line is stored in the first capacitor in response to a select signal from a selecting scan line. The voltage level of the boosting scan line is changed so that the voltage of the first capacitor is changed by coupling of the first and second capacitors. The driving current corresponding to the changed voltage flows to the organic EL element to emit light. As a result, the current flowing to the organic EL element can be controlled using a large data current, and the influence of the parasitic capacitance components of the transistors or data lines can be minimized.

Abstract: An image display device having a reduced data programming time. The image display device includes a plurality of pixel circuits, each said pixel circuit for displaying an image which corresponds to a data current, which is applied thereto. The image display device also includes a plurality of data lines for transmitting the data currents to the pixel circuits, and a plurality of scan lines for transmitting select signals to the pixel circuits. A driver applies a precharge voltage to a corresponding one of the data lines in response to a first control signal, and supplies the corresponding one of the data currents to the corresponding one of the data lines in response to a second control signal.

Abstract: A data current sample and hold circuit having an input terminal of a current source type and an output terminal of a current sink type. The sample and hold circuit includes a first transistor, a capacitor, and a plurality of switches, for sampling and holding the data current sunk to an output terminal of a data driver. When the sampled and held data current is applied to the data line, the data current is sunk to an output terminal of the sample and hold circuit. The sample and hold circuit is used together with a data driver having an output terminal of the current sink type.

Abstract: An organic electroluminescent display and driving method thereof. The organic electroluminescent display includes a demultiplexer for outputting signals provided by a data driver to a plurality of data lines according to on/off operation of analog switches. The driving method divides a frame into two parts, and drives them. Data signals are applied to pixels which are not adjacent among the pixels of each row during the former ½ frame, and the data signals are applied to the pixels to which no data signal has been applied in the former ½ frame during the latter ½ frame.

Abstract: An emission display includes data lines, select signal lines, emit signal lines, and pixel circuits including switches, a transistor, and an emission element. The first switch transmits a data current from the data line in response to a first scan signal from the select signal line, and the capacitor charges a voltage corresponding to the data current from the first switch. The second switch supplies the current from the transistor to the emission element in response to a second scan signal having a first level from the emit signal line during a display period. During a non-display period, the second switch is turned off in response to the second scan signal having a second level, and no current from the transistor is supplied to the emission element.

Abstract: A fastening arrangement of a machine base (8) of a machine on foundations (1). The fastening arrangement includes a foundation recess (3), filled with concrete (71, 72) and having an inner anchor shank (4), a foundation plate (2) of steel on the foundation (1), the machine base (8) on the foundation plate (2), an anti-fatigue bolt/stud bolt (9) restraining the machine against the foundation (1), the anti-fatigue bolt/stud bolt (9) being screwed into the anchor shank (4). The anchor shank (4) has at least two threaded disks (5) arranged offset from one another. The anti-fatigue bolt/stud bolt (9) screwed into the anchor shank (4) is passed through the foundation plate (2) and the machine base (8).

Abstract: Disclosed are an optical module interfacing device for connecting an RJ interface and an SFP type optical module to an SFP type optical module connector without additional processing, and an Ethernet system using the optical module interfacing device, thus supporting data transmission and reception. The optical module interfacing device includes a board having the same dimensions as those of the optical module, a male connector, having the same dimensions as those of the optical module, formed at a side surface of one end of the board to be connected to the female connector for the optical module mounted on a host board, and an RJ female connector provided with a plurality of pins formed on an upper surface of the board, respectively corresponding to pins of the male connector, according to standards. Further, UTP data is provided to MDI supporting ports of a physical layer through an interfacing unit.

Abstract: A buffer circuit includes first to sixth transistors. The first transistor is coupled between a first power source and a first node, and has a gate for receiving a first signal having a first signal level. The second transistor is coupled between the first node and a second power source, and has a gate for receiving a second signal having a second signal level, which is an inverse of the first signal level. The third transistor has a gate coupled to the first node, and is coupled between the first power source and a second node. The fourth transistor is coupled between the second node and the second power source, and has a gate for receiving the first signal. The fifth transistor has a gate coupled to the second node, and is coupled between the first power source and an output end. The sixth transistor has a gate coupled to the first node, and is coupled between the output end and the second power source. In addition, a capacitance is formed between the gate of the sixth transistor and the output end.

Abstract: A memory management apparatus and method for storing data in units of various packet sizes in appliances utilizing memory devices are provided. The memory allocation apparatus includes data memory which includes a plurality of data blocks, each of which includes a plurality of sub data blocks having a predetermined size, and when there is a request for allocating memory space of a variable size, allocates memory space in units of any one of the sub data blocks and the data blocks, a free list memory which manages an free memory space of the data memory as at least one or more lists, and registers that store head location information and tail location information of the list.

Abstract: Provided are a packet scheduling system and method capable of fair link resource distribution among a plurality of sessions requesting transmissions to an identical output link in input and output interfaces of a node in a high-speed packet exchange network such as an ATM network or the Internet. The packet scheduling system uses a traffic classifier which classifies traffic input from a plurality of input links, for each session; a central management unit which manages the agreed speed for each session and the virtual time of a system; a virtual finish time calculation unit which in response to the agreed speed and the system virtual time, calculates the virtual finish time of each packet for the traffic and attaches the calculated virtual finish time to the head of the packet as a time stamp.

Abstract: A massive packet transmitter in a WAN (wide area network) . The transmitter includes: an encoder for segmenting packets for transmission through the WAN into messages having a predetermined length, encoding the respective segmented messages, adding a parity bit to each encoded message to make it into a codeword, and transmitting the codeword/ A decoder is used for receiving the codeword from the encoder through the WAN, correcting an error of the corresponding codeword, and removing a parity bit included in the corresponding codeword to recover the codeword to an original message. Errors generated when transmitting massive packets through the WAN are removed using a FEC method, and massive packets such as a IPv6 jumbogram can be used without errors in the WAN.

Abstract: Provided are an IP address lookup system and method for forwarding a packet over a data plane of a router. The IP address lookup system includes a forwarding table which has a three-layer table architecture so that it can search for each address group that constitutes an IP destination address of an input packet and a forwarding engine which obtains packet processing information and next hop information for the input packet by searching for the forwarding table using the IP destination address as a search key.

Abstract: The present invention is directed to a flat panel display whose brightness is adjusted based on inputted signals. In the flat panel display of the present invention, the pixels of the display panel are formed with capacitors for temporarily storing voltages corresponding to signals applied to the data lines responding to the scan signals applied to the scan lines and the pictures are displayed based on the voltages stored in the capacitors. Also, the display period controller controls a first period for storing a first voltage corresponding to a gray level of a picture to be displayed in the capacitors during one frame and a second period for storing a second voltage representing a black level in the capacitors, depending on a first signal representing a brightness level. Accordingly, the brightness of a variety of levels can be expressed without having to adjust a level of data voltage.

Abstract: In a level shifter, first and second PMOS transistors are connected in series between first and second power sources for supplying first high level and low level voltages, respectively, and a capacitor is formed between a contact point of the first and second transistors and the second transistor's gate. A third PMOS transistor is diode-connected and connected between the first and second transistors' gates. When a second low level voltage is input to the first transistor's gate, a second high level voltage is output to the contact point according to an on resistance ratio of the first and second transistors. When a first high level voltage is input to the first transistor's gate, the second transistor is bootstrapped according to the voltage charged to the capacitor so that a first low level voltage is substantially output to the contact point.

Abstract: In an organic EL display, a scan driver is divided into several scan driving units, and the each scan driving unit includes a plurality of flip-flops and a plurality of buffer units each receiving an output of the flip-flop as an input. The flip-flop includes four NOR gates and the buffer unit includes an OR gate composed of a NOR gate and an inverter, and a buffer composed of two inverters. The NOR gates of the flip-flop and the buffer unit receive a clear signal and are composed of PMOS transistors. When the clear signal of high level is applied to non-operating ones of the scan driving units, outputs of the NOR gates become low level, and thereby, it is possible to remove static currents generated in output terminals of the NOR gates.

Abstract: Disclosed is an image display apparatus having, in every pixel, a light-emitting element such as an organic electro-luminescence (EL) element of which the brightness is controlled by a current. The image display apparatus includes transistors that form a current mirror in the pixel and using a pixel structure having two scan lines, so as to select pixels of at least two rows simultaneously, distribute the current applied to the data line to the pixel for recording display information and the adjacent pixel, and record the display information on the pixel of no more than one row among the selected pixels. This drastically increases the current for driving the data line and decreases the size of the transistors that form the current mirror in the pixel.

Abstract: In a display, capacitors are charged with first precharge voltages at the time of applying selection signals to previous scan lines. A data driver divides a plurality of data lines into a plurality of groups each of which consists of at least one data line and applies corresponding data voltages to the data lines of respective groups sequentially. The display further includes a precharge means, and such precharge means applies second precharge voltages to data lines of at least one group before selection signals for selecting scan line are applied to the scan line connected to the pixel circuits and stops application of the second precharge voltages before corresponding data voltages are applied to the respective groups. In this way, it is possible to solve the problem of poor images due to charge redistribution of the capacitors caused by previous data voltages stored in parasitic capacitors.

Abstract: In an organic EL display, a scan driver is divided into several scan driving units, and the each scan driving unit includes a plurality of flip-flops and a plurality of buffer units each receiving an output of the flip-flop as an input. The flip-flop includes four NOR gates and the buffer unit includes an OR gate composed of a NOR gate and an inverter, and a buffer composed of two inverters. The NOR gates of the flip-flop and the buffer unit receive a clear signal and are composed of PMOS transistors. When the clear signal of high level is applied to non-operating ones of the scan driving units, outputs of the NOR gates become low level, and thereby, it is possible to remove static currents generated in output terminals of the NOR gates.

Abstract: An asynchronous transfer mode (ATM) protection triggering method using “received-AIS” flag determines whether the failure generation position is generated within a protected domain or not, by determining whether the “received-AIS” flag is “0” in case that a node detecting a failure link transmits an end-to-end AIS cell to a downstream side node, and a source point passing the end-to-end AIS cell sets the “received-AIS” flag to “1” and then receives “AIS cell receiving” signal from a sink point of the protected domain, thereby obviating a CRC-10 calculation problem and a backward compatibility.