Patents by Inventor Dong You Kim

Dong You Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8823158
    Abstract: A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: September 2, 2014
    Assignee: SK Hynix Inc.
    Inventors: Jae Sung Oh, Moon Un Hyun, Jong Hyun Kim, Jin Ho Gwon, Dong You Kim, Ki Bon Cha
  • Patent number: 8445166
    Abstract: There is provided a method of fabricating a lithography mask, the method including: forming a transparent polymer layer on a surface of a first substrate where a convex-concave pattern is formed; separating the transparent polymer layer from the first substrate, the transparent polymer layer having a convex-concave surface formed by the convex-concave pattern of the first substrate transferred thereonto; depositing a metal thin film on the convex-concave surface; forming a viscous film on a second substrate; disposing the transparent polymer layer on the second substrate such that the viscous film and metal thin film are partially bonded together; and separating the transparent polymer layer from the second substrate such that a portion of the metal thin film bonded to the viscous film is removed, wherein a metal thin film pattern having the portion of the metal thin film removed therefrom is formed on the convex-concave surface.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: May 21, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Young Song, Dong You Kim, Won Ho Jung, Young Jin Cho, Young Chun Kim
  • Patent number: 8299591
    Abstract: A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: October 30, 2012
    Assignees: Hynix Semiconductor Inc.
    Inventors: Jae Sung Oh, Moon Un Hyun, Jong Hyun Kim, Jin Ho Gwon, Dong You Kim, Ki Bon Cha
  • Patent number: 8110751
    Abstract: The present invention relates to a semiconductor memory module and an electronic component socket for coupling with the same. A printed circuit board of the semiconductor memory module includes three signal pad arrays longitudinally formed in a row on one sides of a first surface, a second surface and a third surface thereof. Each signal pad array includes a plurality of signal pads. An electronic component socket for coupling with the printed circuit board includes thee pin arrays. Thus, an increased number of the signal pads can be provided while retaining the size of the memory module and the electronic component socket.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: February 7, 2012
    Inventors: Dong You Kim, Yong Tae Kyeon, Ja Yong Ku
  • Publication number: 20100243308
    Abstract: The present invention relates to a semiconductor memory module and an electronic component socket for coupling with the same. A printed circuit board of the semiconductor memory module includes three signal pad arrays longitudinally formed in a row on one sides of a first surface, a second surface and a third surface thereof. Each signal pad array includes a plurality of signal pads. An electronic component socket for coupling with the printed circuit board includes thee pin arrays. Thus, an increased number of the signal pads can be provided while retaining the size of the memory module and the electronic component socket.
    Type: Application
    Filed: March 26, 2009
    Publication date: September 30, 2010
    Inventors: DONG YOU KIM, Yong Tae Kyeon, Ja Yong Ku
  • Publication number: 20100072598
    Abstract: A semiconductor package includes a substrate having a substrate body possessing a first region, a second region which is defined around the first region and a third region which is defined around the second region. Wiring lines are placed on the substrate body, and the wiring lines have first ends that extend to the third region. Connection patterns are placed in the third region and are electrically connected to the first ends of the wiring lines. A semiconductor chip is disposed in the first region and is electrically connected to the respective wiring lines, and a molding member is disposed in the first and second regions and covers the semiconductor chip.
    Type: Application
    Filed: December 31, 2008
    Publication date: March 25, 2010
    Inventors: Jae Sung OH, Moon Un HYUN, Jong Hyun KIM, Jin Ho Gwon, Dong You KIM, Ki Bon CHA
  • Publication number: 20100015535
    Abstract: There is provided a method of fabricating a lithography mask, the method including: forming a transparent polymer layer on a surface of a first substrate where a convex-concave pattern is formed; separating the transparent polymer layer from the first substrate, the transparent polymer layer having a convex-concave surface formed by the convex-concave pattern of the first substrate transferred thereonto; depositing a metal thin film on the convex-concave surface; forming a viscous film on a second substrate; disposing the transparent polymer layer on the second substrate such that the viscous film and metal thin film are partially bonded together; and separating the transparent polymer layer from the second substrate such that a portion of the metal thin film bonded to the viscous film is removed, wherein a metal thin film pattern having the portion of the metal thin film removed therefrom is formed on the convex-concave surface.
    Type: Application
    Filed: December 12, 2008
    Publication date: January 21, 2010
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ho Young Song, Dong You Kim, Won Ho Jung, Young Jin Cho, Young Chun Kim
  • Publication number: 20080203552
    Abstract: Disclosed herein is a stacked package. The stacked package includes two or more of a first BGA package and a second BGA package and a circuit board having a circuit pattern. The first BGA package is mounted on one face of the circuit board, and the second BGA package is mounted on the other face of the circuit board. A signal connection member is provided for transmitting signals of the first BGA package and the second BGA package to each other. The second BGA package is provided with a signal connection pad. One end of the signal connection member is bonded to the signal connection pad and the other end of the signal connection member is bonded to the circuit pattern of the circuit board. A method of fabricating the stacked package is also disclosed.
    Type: Application
    Filed: March 8, 2005
    Publication date: August 28, 2008
    Applicant: UNISEMICON CO., LTD.
    Inventors: Dong You Kim, Ki Bon Cha
  • Patent number: 7291906
    Abstract: Disclosed are a stack package and a fabricating method thereof using a ball grid array semiconductor package (hereinafter, referred to as “BGA PKG”). The stack package can easily electrically connect the stacked BGA PKGs with each other by simplifying a stack structure between the BGA PKGs, and increase bonding reliability by improving bonding force bonded portions of solder balls of substrates.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: November 6, 2007
    Inventors: Ki Bon Cha, Dong You Kim
  • Publication number: 20040150107
    Abstract: Disclosed are a stack package and a fabricating method thereof using a ball grid array semiconductor package(hereinafter, referred to as “BGA PKG”). The stack package can easily electrically connect the stacked BGA PKGs with each other by simplifying a stack structure between the BGA PKGs, and increase bonding reliability by improving bonding force bonded portions of solder balls of substrates.
    Type: Application
    Filed: December 29, 2003
    Publication date: August 5, 2004
    Inventors: Ki Bon Cha, Dong You Kim
  • Publication number: 20010045632
    Abstract: A semiconductor chip package and a fabrication method therefor are disclosed. The semiconductor chip package includes a semiconductor chip having a plurality of pads, a passivation film formed on the semiconductor chip and opened in the pads, a metallic film first pattern formed on the upper surfaces of the pads, a metallic film second pattern extended from a corresponding one of the metallic film first patterns formed on one pad among the pads to the passivation film and having a predetermined size which is two times compared to the area of one of the pads, and a plurality of leads formed on the metallic film first pattern.
    Type: Application
    Filed: November 24, 1998
    Publication date: November 29, 2001
    Applicant: Hyundai Electronics Industries Co., Ltd.
    Inventor: DONG-YOU KIM
  • Patent number: 6118174
    Abstract: A bottom lead frame and a bottom lead semiconductor package embodying the invention are capable of forming a multiple row pin structure. The bottom lead frame includes a plurality of first leads, and a plurality of second leads, where each lead has a bottom lead portion and an inner lead portion that is upwardly bent from the bottom lead portion. The first leads and second are arranged on opposite sides of a central portion. Each of the first leads is inserted between a pair of neighboring second leads. The bottom portions of the second leads are arranged outwardly of the bottom portions of the first leads. A lead support bar may be connected to the inner portions of the first and second leads to support the first and second leads. A semiconductor chip may be mounted on upper surfaces of either the first or the second leads.
    Type: Grant
    Filed: December 17, 1997
    Date of Patent: September 12, 2000
    Assignee: LG Semicon Co., Ltd.
    Inventor: Dong-You Kim
  • Patent number: 6010058
    Abstract: In a BGA package having electrically connected active balls and electrically disconnected dummy balls, the active balls are positioned in a radial direction at intervals of 90.degree. around the dummy balls. When a defect occurs in a solder joint, the package can be easily repaired by finding defective active ball; forming a repair hole by using a cutting means at a predetermined portion of the printed circuit board corresponding to a central position between the dummy ball and the defectively soldered active ball; inserting a solder paste injector into the repair hole to inject solder thereinto; and mutually connecting pad extensions of the dummy ball and the defective active ball with the injected solder. Therefore, the overall process can be simplified and its reliability can be improved.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: January 4, 2000
    Assignee: LG Semicon Co., Ltd.
    Inventors: Young-Gon Kim, Dong-You Kim
  • Patent number: 5939776
    Abstract: A lead frame structure of a semiconductor package including a plurality of leads, a respective dam bar extended from at least one of the plurality leads toward an adjacent lead and having a certain distance provided between the respective dam bar and the adjacent lead, and an insulating adhesive member is filled between the leads and the dam bars. The lead frame structure prevents leads from bending or twisting.
    Type: Grant
    Filed: May 13, 1997
    Date of Patent: August 17, 1999
    Assignee: LG Semicon Co., Ltd.
    Inventors: Dong You Kim, Teck Gyu Kang
  • Patent number: 5926380
    Abstract: A lattice of a plurality of individual lead frames allows concurrent or simultaneous molding of a plurality of integrated chips formed in a wafer. The lattice includes a plurality of lead supporting bars arranged in rows and columns and a plurality of leads attached to corresponding ones of the plurality of supporting bars. The plurality of lead supporting bars align with chip partition lines defining each individual integrated chip formed in the wafer. During fabrication, a plurality of individual lead frames is correspondingly attached to a plurality of individual integrated chips formed in a wafer. A plurality of wires are bonded between the plurality of chip pads and the plurality of leads. The wafer is molded such that the plurality of individual lead frames, the plurality of wires, the first surface of the plurality of individual integrated chips and the plurality of chip pads are molded with an epoxy compound with portions of the plurality of leads exposed.
    Type: Grant
    Filed: May 6, 1997
    Date of Patent: July 20, 1999
    Assignee: LG Semicon Co., Ltd.
    Inventor: Dong You Kim
  • Patent number: 5748450
    Abstract: In a BGA package having electrically connected active balls and electrically disconnected dummy balls, the active balls are positioned in a radial direction at intervals of 90.degree. around the dummy balls. When a defect occurs in a solder joint, the package can be easily repaired by finding defective active ball; forming a repair hole by using a cutting means at a predetermined portion of the printed circuit board corresponding to a central position between the dummy ball and the defectively soldered active ball; inserting a solder paste injector into the repair hole to inject solder thereinto; and mutually connecting pad extensions of the dummy ball and the defective active ball with the injected solder. Therefore, the overall process can be simplified and its reliability can be improved.
    Type: Grant
    Filed: April 23, 1996
    Date of Patent: May 5, 1998
    Assignee: LG Semicon Co., Ltd.
    Inventors: Young-Gon Kim, Dong-You Kim