Patents by Inventor Dongao Yang

Dongao Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11979976
    Abstract: Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: May 7, 2024
    Assignee: CelLink Corporation
    Inventors: Kevin Michael Coakley, Malcolm Parker Brown, Dongao Yang, Michael Lawrence Miller, Paul Henry Lego
  • Publication number: 20240098873
    Abstract: Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Applicant: CelLink Corporation
    Inventors: Kevin Michael Coakley, Malcom Parker Brown, Dongao Yang, Michael Lawrence Miller, Paul Henry Lego
  • Publication number: 20210352798
    Abstract: Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.
    Type: Application
    Filed: July 22, 2021
    Publication date: November 11, 2021
    Applicant: CelLink Corporation
    Inventors: Kevin Michael Coakley, Malcolm Parker Brown, Dongao Yang, Michael Lawrence Miller, Paul Henry Lego
  • Patent number: 11116070
    Abstract: Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: September 7, 2021
    Assignee: CELLINK CORPORATION
    Inventors: Kevin Michael Coakley, Malcolm Parker Brown, Dongao Yang, Michael Lawrence Miller, Paul Henry Lego
  • Patent number: 10446956
    Abstract: Provided are electrical harness assemblies and methods of forming such harness assemblies. A harness assembly comprises a conductor trace, comprising a conductor lead with a width-to-thickness ratio of at least 2. This ratio provides for a lower thickness profile and enhances heat transfer from the harness to the environment. In some examples, a conductor trace may be formed from a thin sheet of metal. The same sheet may be used to form other components of the harness. The conductor trace also comprises a connecting end, monolithic with the conductor lead. The width-to-thickness ratio of the connecting end may be less than that of the conductor trace, allowing for the connecting end to be directly mechanically and electrically connected to a connector of the harness assembly. The connecting end may be folded, shaped, slit-rearranged, and the like to reduce its width-to-thickness ratio, which may be close to 1.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: October 15, 2019
    Assignee: CELLINK CORPORATION
    Inventors: Kevin Michael Coakley, Malcolm Brown, Jose Juarez, Dongao Yang
  • Publication number: 20190229449
    Abstract: Provided are electrical harness assemblies and methods of forming such harness assemblies. A harness assembly comprises a conductor trace, comprising a conductor lead with a width-to-thickness ratio of at least 2. This ratio provides for a lower thickness profile and enhances heat transfer from the harness to the environment. In some examples, a conductor trace may be formed from a thin sheet of metal. The same sheet may be used to form other components of the harness. The conductor trace also comprises a connecting end, monolithic with the conductor lead. The width-to-thickness ratio of the connecting end may be less than that of the conductor trace, allowing for the connecting end to be directly mechanically and electrically connected to a connector of the harness assembly. The connecting end may be folded, shaped, slit-rearranged, and the like to reduce its width-to-thickness ratio, which may be close to 1.
    Type: Application
    Filed: April 1, 2019
    Publication date: July 25, 2019
    Applicant: CelLink Corporation
    Inventors: Kevin Michael Coakley, Malcolm Brown, Jose Juarez, Dongao Yang
  • Patent number: 10348009
    Abstract: Provided are electrical harness assemblies and methods of forming such harness assemblies. A harness assembly comprises a conductor trace, comprising a conductor lead with a width-to-thickness ratio of at least 2. This ratio provides for a lower thickness profile and enhances heat transfer from the harness to the environment. In some examples, a conductor trace may be formed from a thin sheet of metal. The same sheet may be used to form other components of the harness. The conductor trace also comprises a connecting end, monolithic with the conductor lead. The width-to-thickness ratio of the connecting end may be less than that of the conductor trace, allowing for the connecting end to be directly mechanically and electrically connected to a connector of the harness assembly. The connecting end may be folded, shaped, slit-rearranged, and the like to reduce its width-to-thickness ratio, which may be close to 1.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: July 9, 2019
    Assignee: CelLink Corporation
    Inventors: Kevin Michael Coakley, Malcolm Brown, Jose Juarez, Dongao Yang
  • Publication number: 20190051999
    Abstract: Provided are electrical harness assemblies and methods of forming such harness assemblies. A harness assembly comprises a conductor trace, comprising a conductor lead with a width-to-thickness ratio of at least 2. This ratio provides for a lower thickness profile and enhances heat transfer from the harness to the environment. In some examples, a conductor trace may be formed from a thin sheet of metal. The same sheet may be used to form other components of the harness. The conductor trace also comprises a connecting end, monolithic with the conductor lead. The width-to-thickness ratio of the connecting end may be less than that of the conductor trace, allowing for the connecting end to be directly mechanically and electrically connected to a connector of the harness assembly. The connecting end may be folded, shaped, slit-rearranged, and the like to reduce its width-to-thickness ratio, which may be close to 1.
    Type: Application
    Filed: October 18, 2018
    Publication date: February 14, 2019
    Applicant: CelLink Corporation
    Inventors: Kevin Michael Coakley, Malcolm Brown, Jose Juarez, Dongao Yang
  • Publication number: 20190021161
    Abstract: Provided are interconnect circuits and methods of forming thereof. A method may involve laminating a substrate to a conductive layer followed by patterning the conductive layer. This patterning operation forms individual conductive portions, which may be also referred to as traces or conductive islands. The substrate supports these portions relative to each other during and after patterning. After patterning, an insulator may be laminated to the exposed surface of the patterned conductive layer. At this point, the conductive layer portions are also supported by the insulator, and the substrate may optionally be removed, e.g., together with undesirable portions of the conductive layer. Alternatively, the substrate may be retained as a component of the circuit and the undesirable portions of the patterned conductive layer may be removed separately. These approaches allow using new patterning techniques as well as new materials for substrates and/or insulators.
    Type: Application
    Filed: July 13, 2018
    Publication date: January 17, 2019
    Applicant: CelLink Corporation
    Inventors: Kevin Michael Coakley, Malcolm Parker Brown, Dongao Yang, Michael Lawrence Miller, Paul Henry Lego
  • Patent number: 10153570
    Abstract: Provided are electrical harness assemblies and methods of forming such harness assemblies. A harness assembly comprises a conductor trace, comprising a conductor lead with a width-to-thickness ratio of at least 2. This ratio provides for a lower thickness profile and enhances heat transfer from the harness to the environment. In some examples, a conductor trace may be formed from a thin sheet of metal. The same sheet may be used to form other components of the harness. The conductor trace also comprises a connecting end, monolithic with the conductor lead. The width-to-thickness ratio of the connecting end may be less than that of the conductor trace, allowing for the connecting end to be directly mechanically and electrically connected to a connector of the harness assembly. The connecting end may be folded, shaped, slit-rearranged, and the like to reduce its width-to-thickness ratio, which may be close to 1.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: December 11, 2018
    Assignee: CelLink Corporation
    Inventors: Kevin Michael Coakley, Malcolm Brown, Jose Juarez, Dongao Yang
  • Publication number: 20180301832
    Abstract: Provided are electrical harness assemblies and methods of forming such harness assemblies. A harness assembly comprises a conductor trace, comprising a conductor lead with a width-to-thickness ratio of at least 2. This ratio provides for a lower thickness profile and enhances heat transfer from the harness to the environment. In some examples, a conductor trace may be formed from a thin sheet of metal. The same sheet may be used to form other components of the harness. The conductor trace also comprises a connecting end, monolithic with the conductor lead. The width-to-thickness ratio of the connecting end may be less than that of the conductor trace, allowing for the connecting end to be directly mechanically and electrically connected to a connector of the harness assembly. The connecting end may be folded, shaped, slit-rearranged, and the like to reduce its width-to-thickness ratio, which may be close to 1.
    Type: Application
    Filed: April 13, 2018
    Publication date: October 18, 2018
    Applicant: CelLink Corporation
    Inventors: Kevin Michael Coakley, Malcolm Brown, Jose Juarez, Dongao Yang