Abstract: Disclosed is a low power consumption switching circuit with voltage isolation function for a PMOS transistor bulk, including a bulk voltage switching control unit, a bulk voltage switching unit, a first voltage input terminal, a second voltage input terminal, and a bulk voltage output terminal. The bulk voltage switching control unit includes a plurality of PMOS transistors and weak pull-down devices, and is configured to generate a control signal to control the bulk voltage switching unit to make the bulk voltage output terminal to be connected to a higher potential between the first voltage input terminal and the second voltage input terminal. The bulk voltage switching unit includes a plurality of PMOS transistors, and is configured to connect bulks of the PMOS transistors to the higher potential between the first voltage input terminal and the second voltage input terminal. Each of the PMOS transistors is a low-withstand-voltage device.

Abstract: Disclosed is a low power consumption switching circuit with voltage isolation function for a PMOS transistor bulk, including a bulk voltage switching control unit, a bulk voltage switching unit, a first voltage input terminal, a second voltage input terminal, and a bulk voltage output terminal. The bulk voltage switching control unit includes a plurality of PMOS transistors and weak pull-down devices, and is configured to generate a control signal to control the bulk voltage switching unit to make the bulk voltage output terminal to be connected to a higher potential between the first voltage input terminal and the second voltage input terminal. The bulk voltage switching unit includes a plurality of PMOS transistors, and is configured to connect bulks of the PMOS transistors to the higher potential between the first voltage input terminal and the second voltage input terminal. Each of the PMOS transistors is a low-withstand-voltage device.

Abstract: A data reading method, a low voltage detection logic circuit, an integrated circuit and a chip are provided. The data reading method includes that: under the condition that a request for reading data from a NonVolatile Memory (NVM) is received, a pre-burnt region return value is read from a preset pre-burnt region of the NVM (S101); whether the pre-burnt region return value is equal to a target pre-burnt value or not is determined (S102); and under the condition that the pre-burnt region return value is equal to the target pre-burnt value, a first control signal is generated, and the first control signal is sent to an NVM controller and the first control signal is used for controlling the VNM controller to read the data from the NVM (S103).

Abstract: A data reading method, a low voltage detection logic circuit, an integrated circuit and a chip are provided. The data reading method includes that: under the condition that a request for reading data from a NonVolatile Memory (NVM) is received, a pre-burnt region return value is read from a preset pre-burnt region of the NVM (S101); whether the pre-burnt region return value is equal to a target pre-burnt value or not is determined (S102); and under the condition that the pre-burnt region return value is equal to the target pre-burnt value, a first control signal is generated, and the first control signal is sent to an NVM controller and the first control signal is used for controlling the VNM controller to read the data from the NVM (S103).