Abstract: The present disclosure provides a voltage-to-time converter and method for reducing parasitic capacitance and power supply influences. The voltage-to-time converter includes: a main sampling network, a compensation sampling network, a discharge network and an over-threshold detection unit. The influence of a traditional VTC parasitic capacitance on a VTC output swing amplitude is reduced by using the compensation sampling network. A sampling common-mode level of the compensation sampling network is compensated, such that the influence of the low-frequency disturbance of a power supply voltage on a threshold of a traditional VTC threshold detection circuit is reduced. The output swing amplitude of the voltage-to-time converter of the present disclosure can reduce the influence of a parasitic capacitance. A voltage common-mode level of a VTC input end is related to a power supply voltage, which reduces a conversion error caused by the influence of the power supply voltage on a threshold.

Abstract: A duty cycle adjustment apparatus comprises a first edge extraction unit for extracting a rising edge of a first clock signal; a locking discrimination unit configured to output a control signal according to a comparison result between a discrimination voltage and a stabilized voltage, and select to connect the first clock signal or the clock output signal; an integration unit, configured to convert the feedback signal into the stabilized voltage, amplify the stabilized voltage to reach a reference voltage, and output a control voltage; a charge pump, configured to output a second clock signal according to the control voltage; a second edge extraction unit, configured to extract a falling edge of the second clock signal; and a phase discriminator, configured to compare a phase of the rising edge of the first clock signal with a phase of the falling edge of the second clock signal to generate the clock output signal.

Abstract: The present disclosure provides a voltage-to-time converter and method for reducing parasitic capacitance and power supply influences. The voltage-to-time converter includes: a main sampling network, a compensation sampling network, a discharge network and an over-threshold detection unit. The influence of a traditional VTC parasitic capacitance on a VTC output swing amplitude is reduced by using the compensation sampling network. A sampling common-mode level of the compensation sampling network is compensated, such that the influence of the low-frequency disturbance of a power supply voltage on a threshold of a traditional VTC threshold detection circuit is reduced. The output swing amplitude of the voltage-to-time converter of the present disclosure can reduce the influence of a parasitic capacitance. A voltage common-mode level of a VTC input end is related to a power supply voltage, which reduces a conversion error caused by the influence of the power supply voltage on a threshold.

Abstract: A highly linear time amplifier with power supply rejection. In a reset stage, the threshold value of an over-threshold detector is used for resetting an output node of an amplifier, to eliminate the impact of power supply voltage changes on the threshold value of the threshold detector. A node capacitor unit is charged under the control of an input clock signal. After completion of charging, the node capacitor unit is discharged under the control of a synchronous clock signal. The time amplification gain only depends on the proportion of the charge and discharge current, and the charging and discharging time are completely linear in principle, which eliminates the nonlinearity of the traditional time amplifier, and reduces the negative impact of threshold change on system performance.

Abstract: The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.

Abstract: The present disclosure provides a clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.

Abstract: The present disclosure relates to the field of semiconductor integrated circuits, and to a method for calibrating a capacitor voltage coefficient of a high-precision successive approximation analog-to-digital converter (SAR ADC). The method includes: calibrating a voltage coefficient; obtaining a sampled charged charge according to a capacitance model with the voltage coefficient; according to an INL value obtained by testing, first verifying whether a maximum value of INL occurs in the place shown in Equation 3, then obtaining two very close second-order capacitor voltage coefficients according to Equation 4, and taking an average value thereof as a second-order capacitor voltage coefficient; and then calibrating the second-order capacitor voltage coefficient in a digital domain.

Abstract: The present disclosure provides a high-speed and low-noise dynamic comparator, which includes: an input unit, including an input NMOS transistor and an input PMOS transistor; a latch unit, including a latching NMOS transistor and a latching PMOS transistor, where the latching NMOS transistor and the latching PMOS transistor are connected to form a latch structure; a pull-up unit, including a pull-up PMOS transistor connected to the input NMOS transistor; and a substrate bootstrap voltage generation circuit, generating a substrate bootstrap voltage.

Abstract: The present disclosure relates to the field of semiconductor integrated circuits, and to a method for calibrating a capacitor voltage coefficient of a high-precision successive approximation analog-to-digital converter (SAR ADC). The method includes: calibrating a voltage coefficient; obtaining a sampled charged charge according to a capacitance model with the voltage coefficient; according to an INL value obtained by testing, first verifying whether a maximum value of INL occurs in the place shown in Equation 3, then obtaining two very close second-order capacitor voltage coefficients according to Equation 4, and taking an average value thereof as a second-order capacitor voltage coefficient; and then calibrating the second-order capacitor voltage coefficient in a digital domain.

Abstract: The present disclosure provides a high-speed and low-noise dynamic comparator, which includes: an input unit, including an input NMOS transistor and an input PMOS transistor; a latch unit, including a latching NMOS transistor and a latching PMOS transistor, where the latching NMOS transistor and the latching PMOS transistor are connected to form a latch structure; a pull-up unit, including a pull-up PMOS transistor connected to the input NMOS transistor; and a substrate bootstrap voltage generation circuit, generating a substrate bootstrap voltage.

Abstract: The present disclosure provides a negative voltage generating circuit having an automatic voltage adjustment function, including a negative voltage generating circuit and a feedback control module. The negative voltage generated by the negative voltage generating circuit is adjusted by the feedback control module. The negative voltage generating circuit having the automatic voltage adjustment function of the present disclosure can automatically adjust the charge current of the charge pump according to the load current, thereby realizing the stability of the output voltage, such that the traditional analog circuit structure can work normally under the extremely low power supply voltage, and is particularly suitable for the deep submicron process. The present disclosure also realizes the digital adjustment of the output voltage, the negative voltage output is no longer single, and can be adjusted according to actual needs.

Abstract: Disclosed is a successive approximation algorithm-based ADC self-correcting circuit, comprising: a coding circuit, a voltage dividing resistor string, a comparator array, a multi-path selection switch, a first digital-to-analog converter, a reference circuit, a control register, and a data register; an input end of the coding circuit is connected to an output end of the comparator array; a positive-phase input end of each comparator in the comparator array is connected to a mobile end of the multi-path selection switch; a negative-phase input end of each comparator in the comparator array is correspondingly connected between each two neighboring resistors in the voltage dividing resistor string; an enabling end of the comparator array is connected to the control register; a first immobile end of the multi-path selection switch is used for receiving an analog signal, a second immobile send is connected to an output end of the first digital-to-analog converter, and a control end is connected to the control regi

Abstract: Disclosed is a successive approximation algorithm-based ADC self-correcting circuit, comprising: a coding circuit, a voltage dividing resistor string, a comparator array, a multi-path selection switch, a first digital-to-analog converter, a reference circuit, a control register, and a data register; an input end of the coding circuit is connected to an output end of the comparator array; a positive-phase input end of each comparator in the comparator array is connected to a mobile end of the multi-path selection switch; a negative-phase input end of each comparator in the comparator array is correspondingly connected between each two neighboring resistors in the voltage dividing resistor string; an enabling end of the comparator array is connected to the control register; a first immobile end of the multi-path selection switch is used for receiving an analog signal, a second immobile send is connected to an output end of the first digital-to-analog converter, and a control end is connected to the control regi

Abstract: The present disclosure provides a negative voltage generating circuit having an automatic voltage adjustment function, including a negative voltage generating circuit and a feedback control module. The negative voltage generated by the negative voltage generating circuit is adjusted by the feedback control module. The negative voltage generating circuit having the automatic voltage adjustment function of the present disclosure can automatically adjust the charge current of the charge pump according to the load current, thereby realizing the stability of the output voltage, such that the traditional analog circuit structure can work normally under the extremely low power supply voltage, and is particularly suitable for the deep submicron process. The present disclosure also realizes the digital adjustment of the output voltage, the negative voltage output is no longer single, and can be adjusted according to actual needs.

Abstract: A high-speed low-power-consumption trigger, which comprises a control signal generation circuit, an enabling unit, and a latch structure. The latch structure comprises two input ends, two output ends, two enabling ends, a second enabling end, and a ground end. The enabling unit comprises two enabling circuits. An output signal X of the control signal generation circuit and an external control signal D serve as input signals of the first enabling circuit. An output end of the first enabling circuit is connected to the first enabling end. The output signal X of the control signal generation circuit and a phase-inverted signal DB of the external control signal D serve as input signals of the second enabling circuit. An output end of the second enabling circuit is connected to the second enabling end.

Abstract: The invention provides a clock delay adjusting circuit based on edge addition and an integrated chip thereof.

Abstract: The present invention provides a device and method for correcting error estimation of an analog-to-digital converter.

Abstract: A high-speed low-power-consumption trigger, which comprises a control signal generation circuit, an enabling unit, and a latch structure. The latch structure comprises two input ends, two output ends, two enabling ends, a second enabling end, and a ground end. The enabling unit comprises two enabling circuits. An output signal X of the control signal generation circuit and an external control signal D serve as input signals of the first enabling circuit. An output end of the first enabling circuit is connected to the first enabling end. The output signal X of the control signal generation circuit and a phase-inverted signal DB of the external control signal D serve as input signals of the second enabling circuit. An output end of the second enabling circuit is connected to the second enabling end.

Abstract: A method for an analog-to-digital converter correcting error estimation includes: according to a correction parameter preset initial value, generating a control signal and finely tuning a digital control delay cell, adjusting a delay amount, and correcting a clock phase error between channels; according to a correction parameter initial value, correcting a gain error between channels, generating and buffering a general correction signal, and triggering a counting cell to start counting, and calling the general correction signal in a buffer and generating a preliminary estimation result by using a cyclic correlation method; when counting to a preset value, setting low-pass filter accumulating cell enable ends and a correction parameter updating cell, generating an error estimation result from the preliminary estimation result and latching it, updating a clock correction parameter and a gain correction parameter according to a gradient descent method, and latching them, and resetting to carry out cyclic estimat

Abstract: The present invention provides a high-precision analog-to-digital converter, includes a redundant weight capacitor array, a comparator, a code reestablishment circuit, a weight storage circuit and a control logic circuit. The redundant weight capacitor array collects input voltages and generates output voltages in a sampling stage. The comparator compares the output voltages of the redundant weight capacitor array. The code reestablishment circuit calculates an output code of the successive approximation type analog-to-digital converter according to the comparator output result and a capacitor weight in the weight storage circuit. The weight storage circuit stores the capacitor weight. The control logic circuit controls the sampling and conversion stages of the redundant weight capacitor array. The present invention also provides a DNL-based performance improvement method adapted to the analog-to-digital converter.