Abstract: An operation circuit of a convolutional neural network is provided. The circuit includes: an external memory configured to store an image to be processed, a direct access element connected with the external memory and configured to read the image to be processed and transmit this image to a control element, the control element connected with the direct access element and configured to store the image to be processed into an internal memory, the internal memory connected with the control element and configured to cache the image to be processed, and at least one operation element connected with the internal memory and configured to read the image to be processed from the internal memory and implement convolution and pooling operations. Through the circuit, the technical problem that a large system bandwidth is occupied due to a large amount of the convolution operation of the convolutional neural network is solved.