Abstract: Disclosed is a semiconductor device comprising a first semiconductor die and a second semiconductor die on the first semiconductor die. The first semiconductor die comprises a first pad, a first dielectric pattern that surrounds a lateral surface of the first pad, and a second dielectric pattern that surrounds a lateral surface of the first dielectric pattern. The second semiconductor die comprises a second pad in contact with the first pad. The first dielectric pattern comprises a first dielectric material. The second dielectric pattern comprises a second dielectric material different from the first dielectric material. A thermal conductivity of the second dielectric material is greater than a thermal conductivity of the first dielectric material.

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a first subsidiary integrated circuit, an upper dielectric layer that covers the first subsidiary integrated circuit, a polishing barrier layer on the upper dielectric layer, a bonding layer on the polishing barrier layer, and a substrate on the bonding layer. The upper dielectric layer and the bonding layer comprise a first material. The polishing barrier layer comprises a second material having a polishing selectivity with respect to the first material.

Abstract: A semiconductor device includes a first semiconductor chip having a first pad structure and a second semiconductor chip having a second pad structure. The first pad structure and the second pad structure are bonded to each other in a first direction. The first pad structure includes a first filling conductive film and a second filling conductive film. The first filling conductive film includes a first portion that overlaps the second filling conductive film in the first direction, and a second portion that overlaps the second filling conductive film in a second direction intersecting the first direction. A first height of the first portion in the first direction is greater than a thickness of the second portion in the second direction, and an electrical conductivity of the second filling conductive film is greater than the electrical conductivity of the first filling conductive film.

Abstract: A semiconductor device may include a first bonding pad having a first width, and a second bonding pad coupled to the first bonding pad and having a second width different from the first width, wherein the first bonding pad includes a first material, and the second bonding pad includes a second material different from the first material.

Abstract: A semiconductor package is provided.

Abstract: A method includes providing a first substrate structure including a first semiconductor substrate having first and second surfaces opposite to each other, and a first semiconductor device layer on the first surface, providing a second substrate structure including a second semiconductor substrate having third and fourth surfaces opposite to each other, and a second semiconductor device layer on the third surface, removing a portion of the second semiconductor device layer on a first edge region of the second semiconductor substrate, electrically connecting the first and second semiconductor device layers by bonding the first and second substrate structures such that the first surface faces the third surface, forming a gap-filling film that fills a portion of a gap between the first substrate structure and the first edge region, removing a portion of the first edge region and reducing the thickness of the second semiconductor substrate using a laser trimming process.

Abstract: A semiconductor device includes a substrate that comprises a first region and a second region; a first wiring structure on the first region of the substrate, wherein the first wiring structure comprises a lower bonding pad; a second wiring structure on the first wiring structure, wherein the second wiring structure comprises an upper bonding pad that contacts the lower bonding pad; a lower alignment pattern on the second region of the substrate, wherein the lower alignment pattern is spaced apart from the lower bonding pad; and an upper alignment pattern on the second region of the substrate, wherein the upper alignment pattern is spaced apart from the upper bonding pad, wherein the lower alignment pattern comprises sub-lower alignment patterns, and wherein the upper alignment pattern comprises sub-upper alignment patterns.

Abstract: A method of fabricating a semiconductor device includes forming a substrate and a wiring layer, forming a first interlayer insulating layer on the wiring layer, forming an etch stop layer covering a portion of an upper surface of the first interlayer insulating layer, forming a compensation insulating layer on the first interlayer insulating layer and the etch stop layer, planarizing the compensation insulating layer to form a compensation insulating pattern, forming a second interlayer insulating layer on the etch stop layer, and bonding the second interlayer insulating layer and a bonding wafer. The planarizing of the compensation insulating layer includes removing a portion of the compensation insulating layer to expose the etch stop layer.

Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

Abstract: An ion beam source including a plasma chamber including a plasma generating space, a plasma generator configured to generate plasma in the plasma generating space, a first grid connected to the plasma chamber, a second grid connected to the plasma chamber, and a first grid driver connected to the first grid. The first grid driver may be configured to move the first grid relative to the second grid.

Abstract: The present disclosure provides a semiconductor device manufacturing method that includes forming a lower chip and an upper chip, and bonding the lower chip and the upper chip to each other. The forming of the lower chip includes providing a lower substrate, sequentially forming a lower interlayer insulating film and a pre-lower adhesive film, etching portions of the pre-lower adhesive film and the lower interlayer insulating film to form a lower trench, forming, using a sputtering process, a first lower seed film and a second lower seed film. The forming of the upper chip includes providing an upper substrate, sequentially forming an upper interlayer insulating film and a pre-upper adhesive film, etching portions of the pre-upper adhesive film and the upper interlayer insulating film to form an upper trench, forming, using the sputtering process, a first upper seed film and a second upper seed film.

Abstract: The described technology relates generally to a material for a metal line in a semiconductor device including an alloy including aluminum as a main material, copper, and an element X, wherein the element X has 1) a coefficient of thermal expansion (CTE) of greater than about 0.55 ppm/K and less than about 5 ppm/K, 2) a melting point (MP) of greater than about 3000° C., and 3) electronegativity of greater than about 2.2, a metal line in a semiconductor device including the alloy, and a method of forming a metal line in a semiconductor device.

Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

Abstract: An ion beam deposition method includes placing a substrate into an ion beam deposition apparatus, irradiating an ion beam from an ion beam source toward a target plate, and rotating the target plate during the irradiating of the ion beam. The target plate includes a first region that includes a first material, and a second region that includes a second material different from the first material.

Abstract: An ion beam source including a plasma chamber including a plasma generating space, a plasma generator configured to generate plasma in the plasma generating space, a first grid connected to the plasma chamber, a second grid connected to the plasma chamber, and a first grid driver connected to the first grid. The first grid driver may be configured to move the first grid relative to the second grid.

Abstract: A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a substrate having a first via hole, an insulation interlayer formed on the substrate and having a first bonding pad in an outer surface thereof and a second via hole connected to the first via hole and exposing the first bonding pad, and a plug structure formed within the first and second via holes to be connected to the first bonding pad. The second semiconductor chip includes a second bonding pad bonded to the plug structure which is exposed from a surface of the substrate of the first semiconductor chip.

Abstract: A bevel etching apparatus includes a chuck plate that is configured to receive a substrate, a lower ring surrounding a circumference of the chuck plate, a cover plate on the chuck plate, and an upper ring surrounding a circumference of the cover plate. The lower ring includes a ring base and a protrusion that extends upwardly from an edge of the ring base and surrounds a lower portion of a sidewall of the substrate.

Abstract: A semiconductor device includes a conductive component on a substrate, a passivation layer on the substrate and including an opening that exposes at least a portion of the conductive component, and a pad structure in the opening and located on the passivation layer, the pad structure being electrically connected to the conductive component. The pad structure includes a lower conductive layer conformally extending on an inner sidewall of the opening, the lower conductive layer including a conductive barrier layer, a first seed layer, an etch stop layer, and a second seed layer that are sequentially stacked, a first pad layer on the lower conductive layer and at least partially filling the opening, and a second pad layer on the first pad layer and being in contact with a peripheral portion of the lower conductive layer located on the top surface of the passivation layer.

Abstract: Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

Abstract: A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.