Patents by Inventor Dongdong JIANG
Dongdong JIANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240061282Abstract: The optical device includes: a first coupler having an adjustable beam splitting ratio; a sensing arm and a programmable modulation arm which are connected to the first coupler; and a second coupler having an input port connected to the sensing arm and the programmable modulation arm and an output port connected to a photodetector. The sensing arm is used for generating, by means of a slot waveguide, a first signal from a first light wave beam outputted by the first coupler. The programmable modulation arm is used for obtaining, by utilizing a grating, a second signal according to a second light wave beam outputted by the first coupler, and the grating is a nano grating generated under a pre-programmed voltage parameter of a programmable piezoelectric transducer of the programmable modulation arm. An electronic device and a programmable photonic integrated circuit are also disclosed herein.Type: ApplicationFiled: September 29, 2021Publication date: February 22, 2024Inventors: Zhe Xu, Chen Li, Dongdong Jiang, Ruyang Li, Yaqian Zhao, Rengang Li
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Patent number: 11830244Abstract: An image recognition method and apparatus based on a systolic array, and a medium are disclosed. The method includes: converting obtained image feature information into a one-dimensional feature vector; converting an obtained weight matrix into a one-dimensional weight vector, and allocating a corresponding weight group to each node in a trained three-dimensional systolic array model; performing multiply-accumulate of the feature vector and a weight value on the one-dimensional feature vector in parallel by using the three-dimensional systolic array model, to obtain a feature value corresponding to each node, the feature values with different values reflecting article categories contained in an image; and determining an article category contained in the image according to the feature value corresponding to each node and a pre-established corresponding relationship between the feature value and the article category.Type: GrantFiled: April 26, 2021Date of Patent: November 28, 2023Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.Inventors: Gang Dong, Yaqian Zhao, Rengang Li, Hongbin Yang, Haiwei Liu, Dongdong Jiang
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Publication number: 20230326199Abstract: An image recognition method and apparatus based on a systolic array, and a medium are disclosed. The method includes: converting obtained image feature information into a one-dimensional feature vector; converting an obtained weight matrix into a one-dimensional weight vector, and allocating a corresponding weight group to each node in a trained three-dimensional systolic array model; performing multiply-accumulate of the feature vector and a weight value on the one-dimensional feature vector in parallel by using the three-dimensional systolic array model, to obtain a feature value corresponding to each node, the feature values with different values reflecting article categories contained in an image; and determining an article category contained in the image according to the feature value corresponding to each node and a pre-established corresponding relationship between the feature value and the article category.Type: ApplicationFiled: April 26, 2021Publication date: October 12, 2023Applicant: Inspur Suzhou Intelligent Technology Co., Ltd.Inventors: Gang DONG, Yaqian ZHAO, Rengang LI, Hongbin YANG, Haiwei LIU, Dongdong JIANG
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Patent number: 11775803Abstract: A system for accelerating an RNN network including: a first cache, which is used for outputting Wx1 to WxN or Wh1 to WhN in parallel in N paths in a cyclic switching manner, and the degree of parallelism is k; a second cache, which is used for outputting xt or ht-1 in the cyclic switching manner; a vector multiplication circuit, which is used for, by using N groups of multiplication arrays, respectively calculating Wx1xt to WxNxt, or respectively calculating Wh1ht-1 to WhNht-1; an addition circuit, which is used for calculating Wx1xt+Wh1ht-1+b1 to WxNxt+WhNht-1+bN; an activation circuit, which is used for performing an activation operation according to an output of the addition circuit; a state updating circuit, which is used for acquiring ct-1, calculating ct and ht, updating ct-1, and sending ht to the second cache; a bias data cache; a vector cache; and a cell state cache.Type: GrantFiled: April 26, 2021Date of Patent: October 3, 2023Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.Inventors: Haiwei Liu, Gang Dong, Yaqian Zhao, Rengang Li, Dongdong Jiang, Hongbin Yang, Lingyan Liang
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Publication number: 20230278862Abstract: The disclosure discloses a synthesis method of hexafluorophosphate, belonging to the technical field of chemical synthesis. The synthesis method of hexafluorophosphate is characterized by comprising the following steps: reacting a phosphorus pentahalide inert solvent solution obtained by dissolving phosphorus pentahalide into an inert solvent with an alkali metal fluoride salt hydrogen fluoride solution obtained by dissolving an alkali metal halide salt into anhydrous hydrogen fluoride in a reactor in a ratio to obtain a mixture consisting of hexafluorophosphate, hydrogen fluoride, the inert solvent and hydrogen halide, performing gas-liquid separation to remove a hydrogen halide gas, then heating and evaporating to recover hydrogen fluoride, finally performing solid-liquid separation to recover the inert solvent, and then drying the solid to obtain hexafluorophosphate.Type: ApplicationFiled: May 12, 2023Publication date: September 7, 2023Inventors: Qiliang YUAN, Jian CHEN, Haifeng CHEN, Pengfei XU, Jianfei ZHU, Dongdong JIANG, Yinhao CHEN, Chao WANG
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Publication number: 20230267740Abstract: A video data processing method, including: obtaining three-dimensional feature data and three-dimensional weight data corresponding to video data; separately preprocessing the three-dimensional feature data and the three-dimensional weight data to obtain a feature value matrix and a weight value matrix; and inputting the feature value matrix and the weight value matrix into a plurality of three-dimensional systolic arrays for parallel computing to obtain a video data processing result. The present method can fully expand the degree of parallelism of computation and a four-dimensional systolic computation architecture is constructed by using multiple three-dimensional systolic arrays, so as to perform parallel computing on a three-dimensional feature value matrix and a three-dimensional weight value matrix, thereby shortening the computation time of three-dimensional convolution, and improving the video data processing efficiency.Type: ApplicationFiled: April 26, 2021Publication date: August 24, 2023Inventors: Gang DONG, Yaqian ZHAO, Rengang LI, Hongbin YANG, Haiwei LIU, Dongdong JIANG
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Patent number: 11698730Abstract: A data storage method, apparatus, and device, and a readable storage medium. The method includes: after a random access memory is powered on, obtaining target data to be stored in a fixed storage address of the random access memory; determining a target transmission mode from a bit value change transmission mode and a bit value fixed transmission mode, wherein the target transmission mode is different from a historical transmission mode determined after the random access memory is powered on last time; and transmitting the target data from and to the random access memory according to the target transmission mode. The method can prevent data from being stolen after power-down of the target data, and guarantees the data security.Type: GrantFiled: January 22, 2021Date of Patent: July 11, 2023Assignee: INSPUR ELECTRONIC INFORMATION INDUSTRY CO., LTD.Inventors: Dongdong Jiang, Yaqian Zhao, Gang Dong, Rengang Li, Haiwei Liu, Hongbin Yang, Chen Li
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Publication number: 20230196068Abstract: A system for accelerating an RNN network including: a first cache, which is used for outputting Wx1 to WxN or Wh1 to WhN in parallel in N paths in a cyclic switching manner, and the degree of parallelism is k; a second cache, which is used for outputting xt or ht-1 in the cyclic switching manner; a vector multiplication circuit, which is used for, by using N groups of multiplication arrays, respectively calculating Wx1xt to WxNxt, or respectively calculating Wh1ht-1 to WhNht-1; an addition circuit, which is used for calculating Wx1xt+Wh1ht-1+b1 to WxNxt+WhNht-1+bN; an activation circuit, which is used for performing an activation operation according to an output of the addition circuit; a state updating circuit, which is used for acquiring ct-1, calculating ct and ht, updating ct-1, and sending ht to the second cache; a bias data cache; a vector cache; and a cell state cache.Type: ApplicationFiled: April 26, 2021Publication date: June 22, 2023Inventors: Haiwei LIU, Gang DONG, Yaqian ZHAO, Rengang LI, Dongdong JIANG, Hongbin YANG, Lingyan LIANG
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Publication number: 20230196500Abstract: Provided are an image data storage method, an image data processing method and system, and a related apparatus. The image data processing method includes the following steps: sequentially storing image data in a dynamic random memory according to a preset storage format, so that adjacent pieces of image data in the dynamic random memory have continuous storage addresses; reading a preset number of pieces of multi-channel parallel image data from the dynamic random memory, and storing the multi-channel parallel image data in a first-in first-out memory of an FPGA; and executing a convolution operation on target image data in the first-in first-out memory to obtain image feature data. By means of the method, the image data processing rate can be increased.Type: ApplicationFiled: January 26, 2021Publication date: June 22, 2023Inventors: Dongdong JIANG, Yaqian ZHAO, Gang DONG, Rengang LI, Haiwei LIU, Hongbin YANG
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Publication number: 20230133665Abstract: A data storage method, apparatus, and device, and a readable storage medium. The method includes: after a random access memory is powered on, obtaining target data to be stored in a fixed storage address of the random access memory; determining a target transmission mode from a bit value change transmission mode and a bit value fixed transmission mode, wherein the target transmission mode is different from a historical transmission mode determined after the random access memory is powered on last time; and transmitting the target data from and to the random access memory according to the target transmission mode. The method can prevent data from being stolen after power-down of the target data, and guarantees the data security.Type: ApplicationFiled: January 22, 2021Publication date: May 4, 2023Inventors: Dongdong JIANG, Yaqian ZHAO, Gang DONG, Rengang LI, Haiwei LIU, Hongbin YANG, Chen LI
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Publication number: 20220135509Abstract: A synthetic method of 9,9-bis[4-(2-hydroxyethoxy)phenyl]fluorene, belonging to the technical field of chemical synthesis. 9-fluorenone, phenoxyethanol, a catalyst and a cocatalyst are stiffed in an alkane solvent and heated until refluxing, the generated water is removed from the reaction solution via an azeotropic method while reacting, the reaction solution is diluted with water after the reaction is ended, uniformly stirred and cooled to separate out crystals and then filtered, a filter cake is rinsed and dried to obtain a 9,9-bis[4-(2-hydroxyethoxy)phenyl]fluorene finished product; the filtered crystallization mother liquor is subjected to standing and layering, a water phase is removed, then an organic phase is distilled to recycle the alkane solvent, and the concentrate is rectified to recycle phenoxyethanol.Type: ApplicationFiled: January 12, 2022Publication date: May 5, 2022Inventors: Qiliang YUAN, Dongdong JIANG, Ying WAN, Yonggen SHI, Pengfei XU, Haifeng CHEN