Abstract: A SoC chip includes: a bus mechanism including at least one MPU; an OTP memory configured to store bus access control information; a mode configuring module connected to at least one MPU and the OTP memory, the mode configuring module being configured to read the bus access control information from the OTP memory when the SoC chip is in a boot mode, and configure the MPU using the bus access control information, and the mode configuring module being further configured to enable the MPU and switch the SoC chip to a user mode upon configuration of the MPU. The bus access control information is stored by using the OTP memory, so that corresponding bus access control information may be written into the OTP memory according to requirements of various application scenarios, thereby being adapted to different application scenarios and having great flexibility.

Abstract: The present disclosure provides a data processing method, a circuit, a terminal device and a storage medium, which includes: generating a decryption keystream of first data according to a physical start address of the first data before or during reading the first data from a flash; and decrypting the first data through the decryption keystream and writing the decrypted first data into a cache, thus the data decryption delay can be reduced.

Abstract: A SoC chip includes: a bus mechanism including at least one MPU; an OTP memory configured to store bus access control information; a mode configuring module connected to at least one MPU and the OTP memory, the mode configuring module being configured to read the bus access control information from the OTP memory when the SoC chip is in a boot mode, and configure the MPU using the bus access control information, and the mode configuring module being further configured to enable the MPU and switch the SoC chip to a user mode upon configuration of the MPU. The bus access control information is stored by using the OTP memory, so that corresponding bus access control information may be written into the OTP memory according to requirements of various application scenarios, thereby being adapted to different application scenarios and having great flexibility.