Abstract: A memory device includes first global bitlines adjacent to a first edge portion of a memory cell region, second global bitlines adjacent to a second edge portion of the memory cell region; dummy global bitlines in a central portion of the memory cell region, and a bitline sense amplifier in a sense amplifier region and connected to the first global bitlines, the second global bitlines, and the dummy global bitlines A first layer of the memory cell region is connected to a second layer of the sense amplifier region and is configured to apply a bias voltage to each of the dummy global bitlines.

Abstract: A memory device includes a first sub wordline driver including a first active region connected to a first wordline through a first direct contact, and a first transistor connected to a first gate line, the first gate line and the first wordline extending in a first direction, and a second sub wordline driver including a second active region connected to a second wordline through a second direct, the second direct contact and first direct contact extending in parallel in a second direction, the second direction being perpendicular to the first direction. A second transistor is connected to a second gate line. The second gate line extends in the first direction. A third wordline driven by a third sub wordline driver is between the first wordline and the second wordline.

Abstract: An embodiment vehicle includes a measurement device configured to measure a voltage by applying an alternating current (AC) voltage to a first part of a positive busbar inside a junction box and detecting waveforms at a negative busbar and a second part of the positive busbar, respectively, and a controller configured to determine whether an error occurs in a connection state or an insulation state of a component of an internal circuit of the junction box or a connecting cable connected to a connector of the junction box by comparing the measured voltage with a reference value measured in advance in a steady state.

Abstract: An encoding method includes: receiving a plurality of messages; encoding the plurality of messages into a polynomial defined by multivariates; and encrypting the polynomial defined by the multivariates to generate a homomorphic ciphertext. The plurality of messages may be multidimensionally packed by using multivariates, and thus, an operation may be performed with low complexity in the process of matrix multiplication for ciphertexts packed with the multivariates.

Abstract: Inorganic particles comprised in an aqueous dispersion according to the present invention consist of agglomerates of crystalline and amorphous microparticles, and exhibit spherical and smooth surfaces. The spherical appearance, low crystallinity, and narrow particle size distribution of the inorganic particles are further advantageous in reducing scratch defects in a CMP process. In addition, since the microparticles on the inorganic particle surfaces provide more active sites and thus the removal rate is high, the inorganic particles may be advantageous as next-generation CMP polishing materials. In addition, the aqueous dispersion according to the present invention further comprises an amino acid, and the amino acid may be adsorbed on a surface of a silicon oxide wafer to strengthen electrostatic attraction between the silicon oxide wafer and the inorganic particles, resulting in an effect of further improving the removal rate.

Abstract: A bit line sense amplifier of a semiconductor memory device includes: sense amplifier blocks including a PMOS driver or an NMOS driver that detects and amplifies a signal difference between a bit line and a complimentary bit line, and sequentially arranged in a bit line extending direction; column selection units that connect the bit line and a local input/output line according to a first column selection signal; complimentary column selection units that connect the complimentary bit line and a complimentary local input/output line according to a second column selection signal; column selection lines that transmit the first column selection signal to each of the column selection units; and complimentary column selection lines that transmit the second column selection signal to each of the complimentary column selection units. The column selection units and the complimentary column selection units may be disposed to be distributed between the sense amplifier blocks.

Abstract: A bit line sense amplifier of a semiconductor memory device includes: sense amplifier blocks including a PMOS driver or an NMOS driver that detects and amplifies a signal difference between a bit line and a complimentary bit line, and sequentially arranged in a bit line extending direction; column selection units that connect the bit line and a local input/output line according to a first column selection signal; complimentary column selection units that connect the complimentary bit line and a complimentary local input/output line according to a second column selection signal; column selection lines that transmit the first column selection signal to each of the column selection units; and complimentary column selection lines that transmit the second column selection signal to each of the complimentary column selection units. The column selection units and the complimentary column selection units may be disposed to be distributed between the sense amplifier blocks.

Abstract: A memory device includes a memory cell array, a row address decoder configured to generate a plurality of main word line driving signals and a plurality of sub word line driving signals, based on an odd signal representing that a main word line driving signal driving an odd word line is activated, generate a plurality of encoded sub word line driving signals used for driving a target word line by outputting the plurality of sub word line driving signals in a first order, and, based on an even signal representing that a main word line driving signal driving an even word line is activated, generate the plurality of encoded sub word line driving signals by outputting the plurality of sub word line driving signals in a second order, and a word line driving circuit configured to drive the target word line at a first voltage level or a second voltage level.

Abstract: The present application relates to a novel compound having inhibitory activity on prostaglandin E2 receptor and uses thereof, and provides a compound represented by formula I, a solvate, stereoisomer or pharmaceutically acceptable salt thereof, a pharmaceutical composition comprising the same, and a method of using the same.

Abstract: A sub word-line driver circuit of a semiconductor memory device includes a first active pattern and a second active pattern in a substrate, and a gate pattern. The first active pattern includes a first drain region and a first source region of a first keeping transistor that precharges a first word-line which is inactive and extends in a first direction with a negative voltage. The second active pattern includes a second drain region and a second source region of a second keeping transistor that precharges a second word-line which is inactive and extends in the first direction with the negative voltage. The gate pattern is on a portion of the first active pattern and on a portion of the second active pattern, partially overlaps the first active pattern and the second active pattern.

Abstract: The present invention provides a bispecific antibody comprising IL-12 or a variant thereof and an antigen binding site that specifically binds to FAP. The bispecific antibody exhibits an anticancer effect by IL-12. In particular, when the anti-FAP antibody is implemented in one antibody, cancer may be efficiently treated by specifically targeting FAP expressed highly in a tumor, and specifically localizing IL-2 to the tumor site. Therefore, the bispecific antibody may be utilized as a pharmaceutical composition for anticancer treatment, and thus has high industrial application potential.

Abstract: The present invention provides a bispecific antibody comprising IL-12 or a variant thereof and an antigen binding site that specifically binds to CD20. The bispecific antibody exhibits an anticancer effect by IL-12. In particular, when the anti-CD20 antibody is implemented in one antibody, IL-12 is specifically localized to a tumor site by targeting CD20, which is specifically expressed in a tumor at a high level, thereby efficiently treating cancer. Therefore, the bispecific antibody can be utilized as a pharmaceutical composition for anticancer treatment, and thus has a high potential for industrial application.

Abstract: A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.

Abstract: An electronic device is provided. The electronic device includes a global positioning system (GPS) module, a communication module, and a processor functionally connected to the GPS module and the communication module. The processor is configured to obtain second location information by refining the first location information, when the second location information is first sensitive information, filter the second location, and when the second location information is not the first sensitive information, convert the second location information into point-of-interest (POI) information on the basis of a mapping table, when the POI information is second sensitive information, filter the POI information, when the POI information is not the second sensitive information, transmit the POI information to an external electronic device through the communication module, and receive update information from the external electronic device in response to the transmission of the POI information.

Abstract: Provided is a fusion protein dimer containing an extracellular domain of CRIg or a fragment thereof, and a protein that specifically binds to VEGF. The protein may not only inhibit complement-related pathways, but also effectively modulate angiogenesis. Therefore, the fusion protein dimer may be effectively used for the treatment and prevention of complement-related diseases, specifically, eye diseases such as macular degeneration, and thus a high possibility of being industrially used.

Abstract: An electronic device may include a wireless communication circuit, a memory, and a processor. The memory may store instructions that allow, when executed, the processor to: obtain context information associated with the state of the electronic device, and contents information being provided by the electronic device; extracting first keywords on the basis of the context information and the contents information; analyze the keyword level for the first keywords; changing the first keywords into a superordinate concept according to preset keyword levels to obtain second keywords; and transmit the second keywords to at least one server by using the wireless communication circuit. Other various embodiments identified through the specification are possible.

Abstract: A sub word-line driver circuit of a semiconductor memory device includes a first active pattern and a second active pattern in a substrate, and a gate pattern. The first active pattern includes a first drain region and a first source region of a first keeping transistor that precharges a first word-line which is inactive and extends in a first direction with a negative voltage. The second active pattern includes a second drain region and a second source region of a second keeping transistor that precharges a second word-line which is inactive and extends in the first direction with the negative voltage. The gate pattern is on a portion of the first active pattern and on a portion of the second active pattern, partially overlaps the first active pattern and the second active pattern.

Abstract: A memory device includes a first sub wordline driver including a first active region connected to a first wordline through a first direct contact, and a first transistor connected to a first gate line, the first gate line and the first wordline extending in a first direction, and a second sub wordline driver including a second active region connected to a second wordline through a second direct, the second direct contact and first direct contact extending in parallel in a second direction, the second direction being perpendicular to the first direction. A second transistor is connected to a second gate line. The second gate line extends in the first direction. A third wordline driven by a third sub wordline driver is between the first wordline and the second wordline.

Abstract: A memory device includes a memory cell array, a row address decoder configured to generate a plurality of main word line driving signals and a plurality of sub word line driving signals, based on an odd signal representing that a main word line driving signal driving an odd word line is activated, generate a plurality of encoded sub word line driving signals used for driving a target word line by outputting the plurality of sub word line driving signals in a first order, and, based on an even signal representing that a main word line driving signal driving an even word line is activated, generate the plurality of encoded sub word line driving signals by outputting the plurality of sub word line driving signals in a second order, and a word line driving circuit configured to drive the target word line at a first voltage level or a second voltage level.

Abstract: A sub-word-line driver and semiconductor memory devices including the same are provided. The sub-word-line driver may include a word line pull-up transistor, a word line pull-down transistor, and a keeping transistor configured to maintain a word line at a specified voltage level. The sub-word-line driver may include a peripheral active region on a substrate, a first peripheral gate electrode that corresponds to a gate node of the word line pull-down transistor on the peripheral active region, a second peripheral gate electrode that corresponds to a gate node of the keeping transistor on the peripheral active region, and a first lower contact coupled to a first region of the peripheral active region. A first (VBB) voltage from the first region may be supplied to a source node of the keeping transistor.