Abstract: A display device includes a display panel including a first non-foldable portion, a second non-foldable portion, and a foldable portion between the first non-foldable portion and the second non-foldable portion, and a barrier layer disposed under the display panel, wherein the barrier layer includes a first barrier layer disposed under the first non-foldable portion, a second barrier layer disposed under the second non-foldable portion, and a plurality of protrusions disposed between the first barrier layer and the second barrier layer and protruding downward from a bottom surface of the foldable portion.

Abstract: A display device includes: a display panel having a non-folding area and a foldable area adjacent to the non-folding area; and a protective film disposed under the display panel, including a polyhedral oligomeric silsesquioxane (POSS) compound, and having a break elongation of about 20% or more.

Abstract: A memory system may include a plurality of first memory devices; and a memory controller that may include a first chip enable (CE) pin configured to output a first CE signal that enables selectively any one of the first memory devices and a first status input pin configured to receive a first output signal indicating a memory operation status of an enabled first memory device from among the first memory devices in a first memory operation status checking period. In the first memory operation status checking period, the first output signal has one of a first level to indicate a first status of the memory operation status of the enabled first memory device, a second level to indicate a second status of the memory operation status of the enabled first memory device, or a third level to indicate a disabled status of the first memory devices.

Abstract: The present invention provides a method of reworking an array substrate including a gate metal layer, a gate insulation layer (G1), a semiconductor layer, a source/drain metal layer, a lower passivation layer, a common electrode layer, an upper passivation layer, and a pixel electrode layer sequentially formed therein. By using a rework mask protecting a jumping passivation hole area in reworking the pixel electrode layer, the method can maintain the electric connection between the common electrode layer and the rework pixel electrode pattern in the jumping passivation hole area even after the pixel electrode rework process, to thereby reduce the occurrence of failure and the reduction of throughput due to the rework process.

Abstract: The present invention provides a Z-inversion type display device comprising a gate line and a data line that intersect with each other to define a pixel area on a substrate, a thin film transistor that includes a gate electrode, a semiconductor layer, a source electrode and a drain electrode, and a pixel electrode that is formed in the pixel area, and is electrically connected to the drain electrode of the thin film transistor, wherein the drain electrode completely overlaps the gate line such that a drain electrode area is wholly included in a gate line area on a plan view.

Abstract: The present invention provides a Z-inversion type display device comprising a gate line and a data line that intersect with each other to define a pixel area on a substrate, a thin film transistor that includes a gate electrode, a semiconductor layer, a source electrode and a drain electrode, and a pixel electrode that is formed in the pixel area, and is electrically connected to the drain electrode of the thin film transistor, wherein the drain electrode completely overlaps the gate line such that a drain electrode area is wholly included in a gate line area on a plan view.

Abstract: The present invention provides a Z-inversion type display device comprising a gate line and a data line that intersect with each other to define a pixel area on a substrate, a thin film transistor that includes a gate electrode, a semiconductor layer, a source electrode and a drain electrode, and a pixel electrode that is formed in the pixel area, and is electrically connected to the drain electrode of the thin film transistor, wherein the drain electrode completely overlaps the gate line such that a drain electrode area is wholly included in a gate line area on a plan view.

Abstract: The present invention provides a method of reworking an array substrate including a gate metal layer, a gate insulation layer (G1), a semiconductor layer, a source/drain metal layer, a lower passivation layer, a common electrode layer, an upper passivation layer, and a pixel electrode layer sequentially formed therein. By using a rework mask protecting a jumping passivation hole area in reworking the pixel electrode layer, the method can maintain the electric connection between the common electrode layer and the rework pixel electrode pattern in the jumping passivation hole area even after the pixel electrode rework process, to thereby reduce the occurrence of failure and the reduction of throughput due to the rework process.

Abstract: The present invention provides a method of reworking an array substrate including a gate metal layer, a gate insulation layer (G1), a semiconductor layer, a source/drain metal layer, a lower passivation layer, a common electrode layer, an upper passivation layer, and a pixel electrode layer sequentially formed therein. By using a rework mask protecting a jumping passivation hole area in reworking the pixel electrode layer, the method can maintain the electric connection between the common electrode layer and the rework pixel electrode pattern in the jumping passivation hole area even after the pixel electrode rework process, to thereby reduce the occurrence of failure and the reduction of throughput due to the rework process.

Abstract: The present invention provides a Z-inversion type display device comprising a gate line and a data line that intersect with each other to define a pixel area on a substrate, a thin film transistor that includes a gate electrode, a semiconductor layer, a source electrode and a drain electrode, and a pixel electrode that is formed in the pixel area, and is electrically connected to the drain electrode of the thin film transistor, wherein the drain electrode completely overlaps the gate line such that a drain electrode area is wholly included in a gate line area on a plan view.

Abstract: The present invention provides a method of reworking an array substrate including a gate metal layer, a gate insulation layer (G1), a semiconductor layer, a source/drain metal layer, a lower passivation layer, a common electrode layer, an upper passivation layer, and a pixel electrode layer sequentially formed therein. By using a rework mask protecting a jumping passivation hole area in reworking the pixel electrode layer, the method can maintain the electric connection between the common electrode layer and the rework pixel electrode pattern in the jumping passivation hole area even after the pixel electrode rework process, to thereby reduce the occurrence of failure and the reduction of throughput due to the rework process.