Abstract: In a method of operating a system-on-chip (SOC), the SOC includes a plurality of processor cores. An operating frequency of the plurality of processor cores is set to a first operating frequency based on permitted power consumption of the SOC and an operating status of the plurality of processor cores. The first operating frequency is within a maximum operating frequency of the plurality of processor cores. At least one of the plurality of processor cores performs at least one processing operation based on the first operating frequency. When present power consumption of the SOC is determined as exceeding the permitted power consumption, a warning signal is activated, and a first control operation for reducing the present power consumption is performed immediately thereafter.

Abstract: In a method of operating a system-on-chip (SOC), the SOC includes a plurality of processor cores. An operating frequency of the plurality of processor cores is set to a first operating frequency based on permitted power consumption of the SOC and an operating status of the plurality of processor cores. The first operating frequency is within a maximum operating frequency of the plurality of processor cores. At least one of the plurality of processor cores performs at least one processing operation based on the first operating frequency. When present power consumption of the SOC is determined as exceeding the permitted power consumption, a warning signal is activated, and a first control operation for reducing the present power consumption is performed immediately thereafter.

Abstract: In a method of operating a system-on-chip (SOC), the SOC includes a plurality of processor cores. An operating frequency of the plurality of processor cores is set to a first operating frequency based on permitted power consumption of the SOC and an operating status of the plurality of processor cores. The first operating frequency is within a maximum operating frequency of the plurality of processor cores. At least one of the plurality of processor cores performs at least one processing operation based on the first operating frequency. When present power consumption of the SOC is determined as exceeding the permitted power consumption, a warning signal is activated, and a first control operation for reducing the present power consumption is performed immediately thereafter.

Abstract: In a method of operating a system-on-chip (SOC), the SOC includes a plurality of processor cores. An operating frequency of the plurality of processor cores is set to a first operating frequency based on permitted power consumption of the SOC and an operating status of the plurality of processor cores. The first operating frequency is within a maximum operating frequency of the plurality of processor cores. At least one of the plurality of processor cores performs at least one processing operation based on the first operating frequency. When present power consumption of the SOC is determined as exceeding the permitted power consumption, a warning signal is activated, and a first control operation for reducing the present power consumption is performed immediately thereafter.

Abstract: In a method of operating a system-on-chip (SOC), the SOC includes a plurality of processor cores. An operating frequency of the plurality of processor cores is set to a first operating frequency based on permitted power consumption of the SOC and an operating status of the plurality of processor cores. The first operating frequency is within a maximum operating frequency of the plurality of processor cores. At least one of the plurality of processor cores performs at least one processing operation based on the first operating frequency. When present power consumption of the SOC is determined as exceeding the permitted power consumption, a warning signal is activated, and a first control operation for reducing the present power consumption is performed immediately thereafter.

Abstract: In a method of operating a system-on-chip (SOC), the SOC includes a plurality of processor cores. An operating frequency of the plurality of processor cores is set to a first operating frequency based on permitted power consumption of the SOC and an operating status of the plurality of processor cores. The first operating frequency is within a maximum operating frequency of the plurality of processor cores. At least one of the plurality of processor cores performs at least one processing operation based on the first operating frequency. When present power consumption of the SOC is determined as exceeding the permitted power consumption, a warning signal is activated, and a first control operation for reducing the present power consumption is performed immediately thereafter.

Abstract: Disclosed herein are a lamination apparatus which adheres substrates to a cover window having a curved surface and a lamination method using the same. The lamination apparatus includes a first jig on which a cover window is mounted, wherein a curved surface portion is formed in the cover window and a curvature center thereof is positioned behind the curved surface portion, a second jig on which a guide member is seated, wherein a substrate is mounted on the guide member and the guide member has a width greater than that of the substrate, and an interference member provided to interfere with both facing front surfaces of the guide member, wherein the interference member interferes with the guide member and the guide member is bent when the second jig approaches the first jig.

Abstract: A negative active material, a negative electrode, a lithium battery including the negative active material, and a method of preparing the negative active material. The negative active material includes a crystalline carbonaceous substrate; and metal oxide nanoparticles disposed on a surface of the crystalline carbonaceous substrate, wherein the metal oxide nanoparticles have a rutile structure. The negative active material may be used to improve high temperature stability and lifespan characteristics of a lithium battery.

Abstract: Disclosed herein are a lamination apparatus which adheres substrates to a cover window having a curved surface and a lamination method using the same. The lamination apparatus includes a first jig on which a cover window is mounted, wherein a curved surface portion is formed in the cover window and a curvature center thereof is positioned behind the curved surface portion, a second jig on which a guide member is seated, wherein a substrate is mounted on the guide member and the guide member has a width greater than that of the substrate, and an interference member provided to interfere with both facing front surfaces of the guide member, wherein the interference member interferes with the guide member and the guide member is bent when the second jig approaches the first jig.

Abstract: A negative active material, a negative electrode, a lithium battery including the negative active material, and a method of preparing the negative active material. The negative active material includes a crystalline carbonaceous substrate; and metal oxide nanoparticles disposed on a surface of the crystalline carbonaceous substrate, wherein the metal oxide nanoparticles have a rutile structure. The negative active material may be used to improve high temperature stability and lifespan characteristics of a lithium battery.

Abstract: A solid electrolyte is disclosed. The solid electrolyte includes a main portion that includes ?-alumina or ??-alumina, and an edge portion integrally provided with the main portion. The edge portion has a mixed portion that includes ?-alumina and includes ? alumina or ??-alumina. A concentration gradient of the ?-alumina in the edge portion decreases in a first direction from the edge portion to the main portion.

Abstract: An electrode structure and an electrochemical cell including the electrode structure are provided. The electrode structure includes a porous three-dimensional (3D) outer net including an interconnected plurality of outer metal lines that define a plurality of outer holes between adjacent ones of the outer metal lines. The outer metal lines include a porous 3D inner net, a first layer coating the inner net, and a second layer coating the first layer. The inner net includes an interconnected plurality of inner metal lines that define a plurality of inner holes between adjacent ones of the inner metal lines. The inner metal lines include a first metal. The first layer includes a second metal. The second layer includes a third metal.

Abstract: In an aspect, an electrode for a rechargeable lithium battery, a method of preparing the same, and a rechargeable lithium battery including the same are provided.

Abstract: A read only memory (ROM) data patch circuit replaces ROM data stored in N modified ROM data blocks with patch data stored in N random access memory (RAM) patch blocks based on patch information. The ROM data patch circuit includes a data patch detecting unit, a RAM address generating unit, and an address selecting unit. The data patch detecting unit generates N offset select signals and an address select signal. The N offset select signals indicate which block a read ROM address belongs to, and the address select signal represents whether the read ROM address belongs to any of the N modified ROM data blocks. The RAM address generating unit generates a read RAM address corresponding to the read ROM address based on the offset select signals. The address selecting unit outputs one of the read ROM address and the read RAM address based on the address select signal.

Abstract: An electrochemical battery including: a housing; a pouch-shaped solid electrolyte disposed in the housing and having an open end; an insulator that is disposed on the open end of the solid electrolyte to cover the open end and includes a plurality of protrusions facing the open end of the solid electrolyte; at least two types of sealants disposed between the solid electrolyte and the insulator and having different glass transition temperatures, respectively; a first electrode material disposed inside the pouch-shaped solid electrolyte; and a second electrode material disposed outside the pouch-shaped solid electrolyte.

Abstract: An electrochemical cell is disclosed. In one embodiment, the cell includes i) a housing comprising first, second and third chambers, wherein the first chamber is interposed between the second and third chambers, ii) a first separator spatially separating the first and second chambers and iii) a second separator spatially separating the first and third chambers.

Abstract: An electrode structure and an electrochemical cell including the electrode structure are provided. The electrode structure includes a porous three-dimensional (3D) outer net including an interconnected plurality of outer metal lines that define a plurality of outer holes between adjacent ones of the outer metal lines. The outer metal lines include a porous 3D inner net, a first layer coating the inner net, and a second layer coating the first layer. The inner net includes an interconnected plurality of inner metal lines that define a plurality of inner holes between adjacent ones of the inner metal lines. The inner metal lines include a first metal. The first layer includes a second metal. The second layer includes a third metal.

Abstract: A solid electrolyte is disclosed. The solid electrolyte includes a main portion that includes ?-alumina or ??-alumina, and an edge portion integrally provided with the main portion. The edge portion has a mixed portion that includes ?-alumina and includes ? alumina or ??-alumina. A concentration gradient of the ?-alumina in the edge portion decreases in a first direction from the edge portion to the main portion.

Abstract: An electrochemical cell includes a housing; a solid electrolyte dividing the housing into a first electrode chamber and a second electrode chamber; a first electrode material accommodated in the first electrode chamber; a second electrode material accommodated in the second electrode chamber; a current collector extending in a first direction in the first electrode chamber; an extended current collector unit extending from the current collector in a second direction; and an electron channel unit on at least one of the current collector and the extended current collector unit.

Abstract: A photosensitive paste composition for forming a black layer on top of plasma display panel (PDP) barrier ribs includes black pigment nanoparticles for contrast enhancement and a cyclic acid anhydride for fundamentally preventing the gelation of the paste composition. The photosensitive paste composition prevents electrical or optical crosstalk between adjacent discharge cells to achieve better contrast. The fundamental prevention of the gelation of the paste composition permits the paste composition to have good storage stability.