Patents by Inventor Dong-ho Hyun
Dong-ho Hyun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8044680Abstract: An on-die termination (ODT) circuit including drive signal generators, each drive signal generator configured to generate a corresponding plurality of ODT drive signals; and ODT drive units, each ODT drive unit configured to terminate a corresponding terminal with a termination resistance in response to the ODT drive signals of a corresponding drive signal generator. The drive signal generators are configured to supply the ODT drive signals to the ODT drive units to output a plurality of ODT control signals through the terminals in a test mode.Type: GrantFiled: May 20, 2009Date of Patent: October 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Ho Hyun, Jin-Sung Kim
-
Publication number: 20090309628Abstract: An on-die termination (ODT) circuit including drive signal generators, each drive signal generator configured to generate a corresponding plurality of ODT drive signals; and ODT drive units, each ODT drive unit configured to terminate a corresponding terminal with a termination resistance in response to the ODT drive signals of a corresponding drive signal generator. The drive signal generators are configured to supply the ODT drive signals to the ODT drive units to output a plurality of ODT control signals through the terminals in a test mode.Type: ApplicationFiled: May 20, 2009Publication date: December 17, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Dong-Ho HYUN, Jin-Sung KIM
-
Patent number: 7612578Abstract: A semiconductor device, a test system and a method of testing an on die termination (ODT) circuit are disclosed. The semiconductor device includes an ODT circuit, a termination impedance control circuit and a boundary scan circuit. The termination impedance control circuit generates termination impedance control signals in response to a test mode command. The ODT circuit is coupled to the plurality of input/output pads and generates a plurality of termination impedances in response to the impedance control signals. The boundary scan circuit stores the termination impedances to output the stored termination impedances. Thus, the semiconductor device may test an ODT circuit accurately by using a smaller number of pins and may reduce a required time for testing the semiconductor device.Type: GrantFiled: October 24, 2006Date of Patent: November 3, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Uk Chang, Dong-Ho Hyun, Seok-Won Hwang
-
Patent number: 7334169Abstract: A memory device includes a plurality of test mode signal generating units and a plurality of test circuits. Each test mode signal generating unit generates a respective test mode signal for a respective test circuit. The test mode signal generating units generate the test mode signals in series for the test circuits. Each test mode signal generating unit may be disposed within a respective test circuit such that wiring is not necessary from the source of the test mode signals to the test circuits.Type: GrantFiled: June 13, 2005Date of Patent: February 19, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Uk Chang, Gil-Shin Moon, Dong-Ho Hyun
-
Patent number: 7230857Abstract: An integrated circuit memory device may include a memory cell array, a plurality of data input/output pins, and a plurality of input/output circuits coupled to respective data input/output pins. The input/output circuits may be configured to accept respective data bits being written to the memory cell array from the respective data input/output pins during a write operation, and the input/output circuits may be configured to provide respective data bits being read from the memory cell array to the respective data input/output pins during a read operation. In addition, the input/output circuits may be configured to modify operational characteristics thereof responsive to respective control bits received through the respective data input/output pins during a mode set operation. Related methods and systems are also discussed.Type: GrantFiled: August 31, 2004Date of Patent: June 12, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-ho Hyun, Seok-won Hwang
-
Publication number: 20070103189Abstract: A semiconductor device, a test system and a method of testing an on die termination (ODT) circuit are disclosed. The semiconductor device includes an ODT circuit, a termination impedance control circuit and a boundary scan circuit. The termination impedance control circuit generates termination impedance control signals in response to a test mode command. The ODT circuit is coupled to the plurality of input/output pads and generates a plurality of termination impedances in response to the impedance control signals. The boundary scan circuit stores the termination impedances to output the stored termination impedances. Thus, the semiconductor device may test an ODT circuit accurately by using a smaller number of pins and may reduce a required time for testing the semiconductor device.Type: ApplicationFiled: October 24, 2006Publication date: May 10, 2007Inventors: Young-Uk Chang, Dong-Ho Hyun, Seok-Won Hwang
-
Publication number: 20060059398Abstract: A memory device includes a plurality of test mode signal generating units and a plurality of test circuits. Each test mode signal generating unit generates a respective test mode signal for a respective test circuit. The test mode signal generating units generate the test mode signals in series for the test circuits. Each test mode signal generating unit may be disposed within a respective test circuit such that wiring is not necessary from the source of the test mode signals to the test circuits.Type: ApplicationFiled: June 13, 2005Publication date: March 16, 2006Inventors: Young-Uk Chang, Gil-Shin Moon, Dong-Ho Hyun
-
Publication number: 20050270854Abstract: An integrated circuit memory device may include a memory cell array, a plurality of data input/output pins, and a plurality of input/output circuits coupled to respective data input/output pins. The input/output circuits may be configured to accept respective data bits being written to the memory cell array from the respective data input/output pins during a write operation, and the input/output circuits may be configured to provide respective data bits being read from the memory cell array to the respective data input/output pins during a read operation. In addition, the input/output circuits may be configured to modify operational characteristics thereof responsive to respective control bits received through the respective data input/output pins during a mode set operation. Related methods and systems are also discussed.Type: ApplicationFiled: August 31, 2004Publication date: December 8, 2005Inventors: Dong-ho Hyun, Seok-won Hwang
-
Patent number: 6911715Abstract: A bipolar transistor in which the occurrence of Kirk effect is suppressed when a high current is injected into the bipolar transistor and a method of fabricating the bipolar transistor are described. The bipolar transistor includes a first collector region of a first conductive type having high impurity concentration, a second collector region of a first conductive type which has high impurity concentration and is formed on the first collector region, a base region of a second conductive type being formed a predetermined portion of the second collector region, and an emitter region of a first conductive type being formed in the base region. The bipolar transistor further includes the third collector region, which has higher impurity concentration than the second collector region, at the bottom of the base region.Type: GrantFiled: September 5, 2003Date of Patent: June 28, 2005Assignee: Fairchild Korea Semiconductor LtdInventors: Chan-ho Park, Jin-myung Kim, Kyeong-seok Park, Dong-ho Hyun
-
Publication number: 20040236132Abstract: Disclosed is a method of preparing a dicyclic phosphorus-melamine compound and a flame retardant for use with a polymer using the same, in which melamine or a melamine derivative is incorporated into a dicyclic phosphorus compound via substitution, whereby the dicyclic phosphorus-melamine compound for actualizing a non-halogen flame retardant is obtained and is advantageous due to its water-insolubility and enhanced impact strenght and tensile strength after treatment due to increased dispersibility, thus having various applications. The method consists of reacting pentaerythritol with phosphorus oxychloride, to synthesize pentaerythritol ester of phosphoro chloridic acid, which is then dissolved in water, to substitute the OH group for the CI group in the ester, followed by the substituted ester with melamine or melamine derivative, to prepare the dicyclic phosphorus-melamine compound.Type: ApplicationFiled: July 1, 2004Publication date: November 25, 2004Inventors: Dae Hee Lee, Dong Ho Hyun, Su Han Gwon, Hyun Deok Cho, Sang Bum Kim
-
Patent number: 6822490Abstract: In a data output circuit for reducing a skewing error of a data signal, a first inversion unit receives a first data signal of an operating voltage level and inverts the received first data signal to obtain a first inverted data signal. If a first power supply voltage of an output voltage level is different from a second power supply voltage with the operating voltage level by at least a predetermined voltage level, a first voltage compensation unit compensates for the voltage level of the first inverted data signal to obtain a first driving signal. A second inversion unit receives a second data signal with the operating voltage level and inverts the received second data signal to obtain a second inverted data signal. If the levels of the first and second power supply voltages are different by at least a predetermined voltage level, a second voltage compensation unit compensates for the voltage level of the second inverted data signal to obtain a second driving signal.Type: GrantFiled: June 30, 2003Date of Patent: November 23, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-ho Hyun, Jong-hyoung Lim
-
Publication number: 20040046186Abstract: A bipolar transistor in which the occurrence of Kirk effect is suppressed when a high current is injected into the bipolar transistor and a method of fabricating the bipolar transistor are described. The bipolar transistor includes a first collector region of a first conductive type having high impurity concentration, a second collector region of a first conductive type which has high impurity concentration and is formed on the first collector region, a base region of a second conductive type being formed a predetermined portion of the second collector region, and an emitter region of a first conductive type being formed in the base region. The bipolar transistor further includes the third collector region, which has higher impurity concentration than the second collector region, at the bottom of the base region.Type: ApplicationFiled: September 5, 2003Publication date: March 11, 2004Inventors: Chan-ho Park, Jin-myung Kim, Kyeong-seok Park, Dong-ho Hyun
-
Publication number: 20040017238Abstract: In a data output circuit for reducing a skewing error of a data signal, a first inversion unit receives a first data signal of an operating voltage level and inverts the received first data signal to obtain a first inverted data signal. If a first power supply voltage of an output voltage level is different from a second power supply voltage with the operating voltage level by at least a predetermined voltage level, a first voltage compensation unit compensates for the voltage level of the first inverted data signal to obtain a first driving signal. A second inversion unit receives a second data signal with the operating voltage level and inverts the received second data signal to obtain a second inverted data signal. If the levels of the first and second power supply voltages are different by at least a predetermined voltage level, a second voltage compensation unit compensates for the voltage level of the second inverted data signal to obtain a second driving signal.Type: ApplicationFiled: June 30, 2003Publication date: January 29, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Dong-Ho Hyun, Jong-Hyoung Lim
-
Patent number: 6617885Abstract: Integrated circuit memory devices according to the present invention include a sense amplifier having a pair of differential input signal lines, a pair of differential output signal lines, and a current amplifier. The current amplifier has an input stage electrically coupled to the pair of differential input signal lines and an output stage electrically coupled to the pair of differential output signal lines. The input stage and/or the output stage are responsive to a first control signal that reduces a gain of the current amplifier when the first control signal is asserted.Type: GrantFiled: July 27, 2001Date of Patent: September 9, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-hyoung Lim, Kyoung-woo Kang, Dong-ho Hyun
-
Publication number: 20020021147Abstract: Integrated circuit memory devices according to the present invention include a sense amplifier having a pair of differential input signal lines, a pair of differential output signal lines, and a current amplifier. The current amplifier has an input stage electrically coupled to the pair of differential input signal lines and an output stage electrically coupled to the pair of differential output signal lines. The input stage and/or the output stage are responsive to a first control signal that reduces a gain of the current amplifier when the first control signal is asserted.Type: ApplicationFiled: July 27, 2001Publication date: February 21, 2002Inventors: Jong-hyoung Lim, Kyoung-woo Kang, Dong-ho Hyun