Abstract: A processing element includes an analog operation circuit configured to receive input data from an input buffer and to generate one or more output currents associated with a multiplication operation of the input data and weights based on a bit-precision of stored weights, one or more analog-to-digital converters (ADCs) each configured to convert the one or more output currents into one or more digital codes, and a digital operation circuit configured to perform an addition operation using the one or more digital codes based on the bit-precision of the weight and to perform a summation operation on a resultant value of the addition operation based on a bit-precision of the input data.