Abstract: An embodiment apparatus for predicting traffic flow on a new road includes a memory, an input device, and a controller configured to input traffic data corresponding to a default context of the new road received by the input device to a prediction model stored in the memory, training of which is completed, and to predict a traffic flow corresponding to various contexts of the new road based on the prediction model.

Abstract: A three-dimensional semiconductor device may comprise a first cell region, a second cell region, and a via plug region disposed between the first cell region and the second cell region; a word line stack disposed in the first cell region, the via plug region, and the second cell region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers which are alternately stacked; and a plurality of via plugs exclusively connected to the plurality of the word lines, respectively, by vertically penetrating through the word line stack in the via plug region. The via plugs may have an arrangement of a zigzag pattern in a row direction from a top view. The diameters of the via plugs may increase in the row direction.

Abstract: A memory may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a row control circuit. The second wafer may include a second logic structure including a column control circuit.

Abstract: A three-dimensional semiconductor device may comprise a first cell region, a second cell region, and a via plug region disposed between the first cell region and the second cell region; a word line stack disposed in the first cell region, the via plug region, and the second cell region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers which are alternately stacked; and a plurality of via plugs exclusively connected to the plurality of the word lines, respectively, by vertically penetrating through the word line stack in the via plug region. The via plugs may have an arrangement of a zigzag pattern in a row direction from a top view. The diameters of the via plugs may increase in the row direction.

Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.

Abstract: A memory device includes: a first wafer including a first substrate, a plurality of first electrode layers and a plurality of first interlayer dielectric layers alternately stacked along first vertical channels projecting in a vertical direction on a top surface of the first substrate, and a dielectric stack comprising a plurality of dielectric layers and the plurality of first interlayer dielectric layers alternately stacked on the top surface of the first substrate; and a second wafer disposed on the first wafer, and including a second substrate, and a plurality of second electrode layers that are alternately stacked with a plurality of second interlayer dielectric layers along second vertical channels projecting in the vertical direction on a bottom surface of the second substrate and have pad parts overlapping with the dielectric stack in the vertical direction.

Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.

Abstract: A memory may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a row control circuit. The second wafer may include a second logic structure including a column control circuit.

Abstract: A memory device is disclosed. The disclosed memory device may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a column control circuit. The second wafer may include a second logic structure including a row control circuit.

Abstract: A three-dimensional semiconductor device may comprise a first cell region, a second cell region, and a via plug region disposed between the first cell region and the second cell region; a word line stack disposed in the first cell region, the via plug region, and the second cell region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers which are alternately stacked; and a plurality of via plugs exclusively connected to the plurality of the word lines, respectively, by vertically penetrating through the word line stack in the via plug region. The via plugs may have an arrangement of a zigzag pattern in a row direction from a top view. The diameters of the via plugs may increase in the row direction.

Abstract: A memory device having a vertical structure includes a memory cell array defined in a cell wafer, and having a plurality of word lines extending in a first direction and arranged in a second direction, and having a plurality of bit lines extending in the second direction and arranged in the first direction; and a logic circuit configured to control the memory cell array, and including a page buffer low-voltage circuit, a page buffer high-voltage circuit, a row decoder circuit and a peripheral circuit, wherein the page buffer low-voltage circuit is disposed in a first peripheral wafer and the page buffer high-voltage circuit, the row decoder circuit and the peripheral circuit are disposed in a second peripheral wafer, and wherein the cell wafer overlaps with the first peripheral wafer and the second peripheral wafer in a vertical direction that is perpendicular to a plane formed by the first direction and the second direction.

Abstract: A memory device includes a cell wafer including a memory cell array; a first logic wafer bonded to one surface of the cell wafer, and including a first logic circuit which controls the memory cell array; and a second logic wafer bonded to the other surface of the cell wafer which faces away from the one surface, and including a second logic circuit which controls the memory cell array.

Abstract: A memory device having a vertical structure includes a memory cell array defined in a cell wafer, and having a plurality of word lines extending in a first direction and arranged in a second direction, and having a plurality of bit lines extending in the second direction and arranged in the first direction; and a logic circuit configured to control the memory cell array, and including a page buffer low-voltage circuit, a page buffer high-voltage circuit, a row decoder circuit and a peripheral circuit, wherein the page buffer low-voltage circuit is disposed in a first peripheral wafer and the page buffer high-voltage circuit, the row decoder circuit and the peripheral circuit are disposed in a second peripheral wafer, and wherein the cell wafer overlaps with the first peripheral wafer and the second peripheral wafer in a vertical direction that is perpendicular to a plane formed by the first direction and the second direction.

Abstract: A memory device includes: a first wafer including a first substrate, a plurality of first electrode layers and a plurality of first interlayer dielectric layers alternately stacked along first vertical channels projecting in a vertical direction on a top surface of the first substrate, and a dielectric stack comprising a plurality of dielectric layers and the plurality of first interlayer dielectric layers alternately stacked on the top surface of the first substrate; and a second wafer disposed on the first wafer, and including a second substrate, and a plurality of second electrode layers that are alternately stacked with a plurality of second interlayer dielectric layers along second vertical channels projecting in the vertical direction on a bottom surface of the second substrate and have pad parts overlapping with the dielectric stack in the vertical direction.

Abstract: A memory device includes a first memory block defined in a first wafer; and a second memory block defined in a second wafer that is disposed in a vertical direction with respect to the first wafer. A size of the first memory block is smaller than a size of the second memory block.

Abstract: A memory device includes a cell wafer including a memory cell array; a first logic wafer bonded to one surface of the cell wafer, and including a first logic circuit which controls the memory cell array; and a second logic wafer bonded to the other surface of the cell wafer which faces away from the one surface, and including a second logic circuit which controls the memory cell array.

Abstract: A memory device includes a first memory block defined in a first wafer; and a second memory block defined in a second wafer that is disposed in a vertical direction with respect to the first wafer. A size of the first memory block is smaller than a size of the second memory block.

Abstract: A memory device is disclosed. The disclosed memory device may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a column control circuit. The second wafer may include a second logic structure including a row control circuit.

Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a memory cell array including a plurality of memory cells, page buffers coupled to the memory cell array through respective bit lines and a control logic configured to control so that, during a read operation, data stored in the memory cell array is sensed and stored in the page buffers, and the data stored in the page buffers is output to an external device, wherein the control logic controls a time point at which a discharge operation is to be performed after the sensing of the data, and a time point at which a data transfer operation between latches included in each of the page buffers is to be performed, in response to a read command received from the external device.

Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a memory cell array including a plurality of memory cells, page buffers coupled to the memory cell array through respective bit lines and a control logic configured to control so that, during a read operation, data stored in the memory cell array is sensed and stored in the page buffers, and the data stored in the page buffers is output to an external device, wherein the control logic controls a time point at which a discharge operation is to be performed after the sensing of the data, and a time point at which a data transfer operation between latches included in each of the page buffers is to be performed, in response to a read command received from the external device.