Abstract: A unit page buffer block includes first to fourth page buffer pairs. Each of the page buffer pairs includes a common column decoder block; and an upper page buffer stage and a lower page buffer stage electrically and commonly connected to the common column decoder block. Each of the upper page buffer stages includes an upper selection block; an upper latch block; and an upper cache block. Each of the lower page buffer stage includes a lower selection block; a lower latch block; and a lower cache block. Each of the upper selection blocks includes first to fourth sub-selection blocks. Each of the upper and lower latch blocks includes first to twelfth upper sub-latch blocks. Each of the upper and lower cache blocks includes first to twelfth upper sub-cache blocks. Each of the common column decoder block includes first to third sub-common column decoder blocks arranged in a row direction.

Abstract: Provided is a negative electrode active material for a lithium secondary battery which includes: a silicon-silicon oxide-magnesium silicate composite comprising a silicon oxide (SiOx, 0<x?2) matrix; and silicon (Si) crystal grains, MgSiO3 crystal grains and Mg2SiO4 crystal grains present in the silicon oxide matrix, wherein the MgSiO3 crystal grains have a crystal size of 5-30 nm and the Mg2SiO4 crystal grains have a crystal size of 20-100 nm in the silicon-silicon oxide-magnesium silicate composite, and the content ratio of MgSiO3 crystal grains to Mg2SiO4 crystal grains is 2:1-1:1 on the weight basis. A method for preparing the negative electrode active material for a lithium secondary battery is also provided.

Abstract: A three-dimensional semiconductor device may comprise a first cell region, a second cell region, and a via plug region disposed between the first cell region and the second cell region; a word line stack disposed in the first cell region, the via plug region, and the second cell region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers which are alternately stacked; and a plurality of via plugs exclusively connected to the plurality of the word lines, respectively, by vertically penetrating through the word line stack in the via plug region. The via plugs may have an arrangement of a zigzag pattern in a row direction from a top view. The diameters of the via plugs may increase in the row direction.

Abstract: A memory may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a row control circuit. The second wafer may include a second logic structure including a column control circuit.

Abstract: A multi-path routing telematics system and method are provided. The method includes receiving, by a controller, a route request from a navigation device and connecting to one or more route-providing servers based on corresponding plug-ins. In addition, the controller is configured to collect routes and transmit them to the navigation device. The route-providing servers are each configured to create a route pursuant to the route request.