Patents by Inventor Dongjiang SUN

Dongjiang SUN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10775668
    Abstract: Disclosed are a backlight module, a display panel, and a display device. The backlight module includes a module frame and at least one first conductive tip structure disposed inside the module frame, the first conductive tip structure includes a first conductive tip, the first conductive tip being in an exposed state of being exposed out from the module frame. The backlight module, according to a point discharge principle, preferentially performs discharging on static electricity through the conductive tip structure, to provide a novel antistatic backlight module.
    Type: Grant
    Filed: January 22, 2017
    Date of Patent: September 15, 2020
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Zijin Lin, Xiaoguang Pei, Haisheng Zhao, Dongjiang Sun
  • Patent number: 10297449
    Abstract: A method for manufacturing thin film transistor, a method for manufacturing array substrate, an array substrate and a display device are provided. The method for manufacturing thin film transistor includes forming an intermediate layer on a substrate, patterning the intermediate layer to form an intermediate layer reserved region and an intermediate layer unreserved region, where the intermediate layer unreserved region corresponds to a pattern of a first structure layer, forming, on the substrate with a pattern of the intermediate layer, a material layer from which the first structure layer is formed, and removing the intermediate layer, and forming the pattern of the first structure layer through a portion of the material layer remaining on the substrate.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: May 21, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zijin Lin, Haisheng Zhao, Xiaoguang Pei, Zhilong Peng, Dongjiang Sun
  • Publication number: 20180331131
    Abstract: A method for manufacturing thin film transistor, a method for manufacturing array substrate, an array substrate and a display device are provided. The method for manufacturing thin film transistor includes forming an intermediate layer on a substrate, patterning the intermediate layer to form an intermediate layer reserved region and an intermediate layer unreserved region, where the intermediate layer unreserved region corresponds to a pattern of a first structure layer, forming, on the substrate with a pattern of the intermediate layer, a material layer from which the first structure layer is formed, and removing the intermediate layer, and forming the pattern of the first structure layer through a portion of the material layer remaining on the substrate.
    Type: Application
    Filed: May 9, 2016
    Publication date: November 15, 2018
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zijin LIN, Haisheng ZHAO, Xiaoguang PEI, Zhilong PENG, Dongjiang SUN
  • Publication number: 20180164641
    Abstract: Disclosed are a backlight module, a display panel, and a display device. The backlight module includes a module frame and at least one first conductive tip structure disposed inside the module frame, the first conductive tip structure includes a first conductive tip, the first conductive tip being in an exposed state of being exposed out from the module frame. The backlight module, according to a point discharge principle, preferentially performs discharging on static electricity through the conductive tip structure, to provide a novel antistatic backlight module.
    Type: Application
    Filed: January 22, 2017
    Publication date: June 14, 2018
    Applicants: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Zijin Lin, Xiaoguang Pei, Haisheng Zhao, Dongjiang Sun
  • Patent number: 9960196
    Abstract: An array substrate includes a gate line, a common electrode line, a common electrode and a pixel electrode arranged on a base substrate. The common electrode is electrically connected to the common electrode line through a common electrode via-hole, and the common electrode includes a hollowed-out portion and a reserved portion at a region corresponding to the common electrode via-hole. The reserved portion is arranged between the gate line adjacent to the common electrode line and the pixel electrode adjacent to the common electrode line, and electrically connected to the common electrode line through the common electrode via-hole. The reserved portion does not overlap the gate line or the pixel electrode. The hollowed-out portion is at least arranged at a side of the reserved portion adjacent to the gate line and/or pixel electrode and between the reserved portion and the gate line and/or the pixel electrode.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: May 1, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Lei Zhang, Jiapeng Li, Jing Zhang, Lei Chen, Dongjiang Sun
  • Publication number: 20180026057
    Abstract: An array substrate includes a gate line, a common electrode line, a common electrode and a pixel electrode arranged on a base substrate. The common electrode is electrically connected to the common electrode line through a common electrode via-hole, and the common electrode includes a hollowed-out portion and a reserved portion at a region corresponding to the common electrode via-hole. The reserved portion is arranged between the gate line adjacent to the common electrode line and the pixel electrode adjacent to the common electrode line, and electrically connected to the common electrode line through the common electrode via-hole. The reserved portion does not overlap the gate line or the pixel electrode. The hollowed-out portion is at least arranged at a side of the reserved portion adjacent to the gate line and/or pixel electrode and between the reserved portion and the gate line and/or the pixel electrode.
    Type: Application
    Filed: July 12, 2017
    Publication date: January 25, 2018
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Lei ZHANG, Jiapeng LI, Jing ZHANG, Lei CHEN, Dongjiang SUN
  • Publication number: 20170373099
    Abstract: Disclosed are an array substrate, a manufacturing method thereof, and a display device. The array substrate includes a gate insulating layer, an active layer, source-drain electrodes, a first conductive layer and an isolation insulating layer), the source-drain electrodes are in contact with the active layer, the gate insulating layer is located on a surface of the active layer, the isolation insulating layer) is located on another surface of the active layer, and the isolation insulating layer at least includes a first hollow structure in a contacting region of the active layer and the source-drain electrodes; the isolation insulating layer is configured to isolate residue of the active layer located outside a region where the first hollow structure is located from contacting the first conductive layer.
    Type: Application
    Filed: August 4, 2016
    Publication date: December 28, 2017
    Inventors: Zijin LIN, Haisheng ZHAO, Zhilong PENG, Dongjiang SUN