Abstract: Computing system enhancements make container instantiation faster, reduce layer content storage demands, and make more container image formats available. A container instantiation location sends a container image pull request to a container registry, receives an image manifest, sends a layer mount request to the registry instead of a layer content download request, receives a layer mount, optionally repeats for additional layers, creates a union file system spanning the layers, and launches a container process based on the union file system without first downloading all the layer content.

Abstract: Local interconnect structures and fabrication methods are provided. A dielectric layer can be formed on a semiconductor substrate. A first film layer can be patterned on the dielectric layer to define a region surrounded by a local interconnect structure to be formed. A sidewall spacer can be formed and patterned surrounding the first film layer on an exposed surface portion of the dielectric layer. A second film layer can be formed on the exposed surface portion of the dielectric layer and can have a top surface substantially flushed with a top surface of the sidewall spacer. The patterned sidewall spacer can be removed to form a first opening. After forming the first opening, the dielectric layer can be etched to form a second opening through the dielectric layer. The second opening can be filled with a conductive material to form the local interconnect structure.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a to-be-etched layer; and forming a hard mask layer on the to-be-etched layer. The method also includes forming a photoresist layer on the hard mask layer; and forming a patterned photoresist layer having openings exposing the hard mask layer by exposing and developing the photoresist layer. Further, the method includes forming sidewall spacers on side surfaces of the openings; and forming a patterned hard mask layer by etching the hard mask layer using the patterned photoresist layer and the sidewall spacers as an etching mask such that patterns in the hard mask layer have a substantially right angle at edge. Further, the method also includes forming to-be-etched patterns by etching the to-be-etched layer based on the patterned hard mask layer.

Abstract: Various embodiments provide shallow trenches and fabrication methods. In an exemplary method, a semiconductor substrate can be provided. A mask layer can be provided on the semiconductor substrate. An etch-cleaning process can be performed. The etch-cleaning process can include etching the semiconductor substrate to form a shallow trench by one or more etching steps using the mask layer as an etch mask. The etch-cleaning process can further include performing a plasma cleaning process after each of the one or more etching steps. The plasma cleaning process can use a plasma that is electronegative.

Abstract: This disclosure relates to a post-etch treating method. An opening is formed by etching a stacked structure of a dielectric layer, an intermediate layer and a metal hard mask layer arranged in order from bottom to top. The treating method sequentially comprises steps of: performing a first cleaning process on the stacked structure with the opening so as to remove at least a part of the metal hard mask layer; and performing a second cleaning process on the stacked structure with the opening so as to remove etching residues.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a to-be-etched layer; and forming a hard mask layer on the to-be-etched layer. The method also includes forming a photoresist layer on the hard mask layer; and forming a patterned photoresist layer having openings exposing the hard mask layer by exposing and developing the photoresist layer. Further, the method includes forming sidewall spacers on side surfaces of the openings; and forming a patterned hard mask layer by etching the hard mask layer using the patterned photoresist layer and the sidewall spacers as an etching mask such that patterns in the hard mask layer have a substantially right angle at edge. Further, the method also includes forming to-be-etched patterns by etching the to-be-etched layer based on the patterned hard mask layer.

Abstract: Various embodiments provide shallow trenches and fabrication methods. In an exemplary method, a semiconductor substrate can be provided. A mask layer can be provided on the semiconductor substrate. An etch-cleaning process can be performed. The etch-cleaning process can include etching the semiconductor substrate to form a shallow trench by one or more etching steps using the mask layer as an etch mask. The etch-cleaning process can further include performing a plasma cleaning process after each of the one or more etching steps. The plasma cleaning process can use a plasma that is electronegative.

Abstract: A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate; and configuring a channel region along a first direction. The method also includes forming trenches at both sides of the channel region along a second direction; and forming a magnetic material layer in each of the trenches. Further, the method includes magnetizing the magnetic material layers to form a magnetic field in the channel region between adjacent magnetic material layers; and forming source/drain regions at both ends of the channel region along the first direction.

Abstract: Local interconnect structures and fabrication methods are provided. A dielectric layer can be formed on a semiconductor substrate. A first film layer can be patterned on the dielectric layer to define a region surrounded by a local interconnect structure to be formed. A sidewall spacer can be formed and patterned surrounding the first film layer on an exposed surface portion of the dielectric layer. A second film layer can be formed on the exposed surface portion of the dielectric layer and can have a top surface substantially flushed with a top surface of the sidewall spacer. The patterned sidewall spacer can be removed to form a first opening. After forming the first opening, the dielectric layer can be etched to form a second opening through the dielectric layer. The second opening can be filled with a conductive material to form the local interconnect structure.

Abstract: A method is provided for fabricating a transistor. The method includes providing a semiconductor substrate; and configuring a channel region along a first direction. The method also includes forming trenches at both sides of the channel region along a second direction; and forming a magnetic material layer in each of the trenches. Further, the method includes magnetizing the magnetic material layers to form a magnetic field in the channel region between adjacent magnetic material layers; and forming source/drain regions at both ends of the channel region along the first direction.

Abstract: The present disclosure relates to a method of fabricating semiconductor devices. In the method provided by the present invention, by filling with diblock copolymer a recess of an interlayer dielectric layer naturally formed between two gate lines and then performing a self-assembly process of the diblock copolymer, a small-sized contact hole precisely aligned with an doped area can be formed, and thus misalignment between the contact hole and the doped area can be eliminated or alleviated.

Abstract: The present invention discloses a method of fabricating a semiconductor device. In the present invention, after the formation of a photo-resist mask on a substrate, the photo-resist is subjected to a plasma pre-treatment, and then etch is conducted. With the plasma pre-treatment, a line width roughness of a linear pattern of the photo-resist can be improved, and thus much better linear patterns can be formed on the substrate during the subsequent etching steps.

Abstract: A method for post-etching treatment of copper interconnecting wires that are used to electrically couple an upper interconnecting layer with a lower interconnecting layer includes forming the lower interconnecting layer on a substrate, and forming the upper interconnecting layer on the lower interconnecting layer. The lower interconnecting layer includes a first dielectric layer, a plurality of wire trenches formed in the first dielectric layer and being filled with copper, and a first top barrier layer overlying the first dielectric layer and the wire trenches. The upper interconnecting layer includes a second dielectric layer on the top barrier layer, and a plurality of vias extending through the second dielectric layer and the top barrier layer and exposing the copper in the wire trenches. The method further includes treating the exposed copper using a plasma process comprising NH3.

Abstract: The present disclosure relates to a method of fabricating semiconductor devices. In the method provided by the present invention, by filling with diblock copolymer a recess of an interlayer dielectric layer naturally formed between two gate lines and then performing a self-assembly process of the diblock copolymer, a small-sized contact hole precisely aligned with an doped area can be formed, and thus misalignment between the contact hole and the doped area can be eliminated or alleviated.

Abstract: This disclosure relates to a post-etch treating method. An opening is formed by etching a stacked structure of a dielectric layer, an intermediate layer and a metal hard mask layer arranged in order from bottom to top. The treating method sequentially comprises steps of: performing a first cleaning process on the stacked structure with the opening so as to remove at least a part of the metal hard mask layer; and performing a second cleaning process on the stacked structure with the opening so as to remove etching residues.

Abstract: The present invention discloses a method of fabricating a semiconductor device. In the present invention, after the formation of a photo-resist mask on a substrate, the photo-resist is subjected to a plasma pre-treatment, and then etch is conducted. With the plasma pre-treatment, a line width roughness of a linear pattern of the photo-resist can be improved, and thus much better linear patterns can be formed on the substrate during the subsequent etching steps.

Abstract: A method for post-etching treatment of copper interconnecting wires that are used to electrically couple an upper interconnecting layer with a lower interconnecting layer includes forming the lower interconnecting layer on a substrate, and forming the upper interconnecting layer on the lower interconnecting layer. The lower interconnecting layer includes a first dielectric layer, a plurality of wire trenches formed in the first dielectric layer and being filled with copper, and a first top barrier layer overlying the first dielectric layer and the wire trenches. The upper interconnecting layer includes a second dielectric layer on the top barrier layer, and a plurality of vias extending through the second dielectric layer and the top barrier layer and exposing the copper in the wire trenches. The method further includes treating the exposed copper using a plasma process comprising NH3.