Abstract: A multilayer ceramic capacitor includes a body having a dielectric layer and internal electrodes disposed to be alternately exposed to the third and fourth surfaces with the dielectric layer interposed therebetween. External electrodes include connection parts respectively formed on opposing surfaces of the body, band parts formed to extend from the connection parts to portions of side surfaces of the body, and corner parts in which the connection parts and the band parts are contiguous. A thickness of each of the external electrodes may be 50 nm to 2 ?m. The external electrodes may be formed using a barrel-type sputtering method. A ratio t2/t1 may satisfy 0.7 to 1.2, where t1 is a thickness of each connection part and t2 is a thickness of each band part. A ratio t3/t1 may satisfy 0.7 to 1.0, where t3 is a thickness of each corner part.

Abstract: A multilayer ceramic capacitor includes a body having a dielectric layer and internal electrodes disposed to be alternately exposed to the third and fourth surfaces with the dielectric layer interposed therebetween. External electrodes include connection parts respectively formed on opposing surfaces of the body, band parts formed to extend from the connection parts to portions of side surfaces of the body, and corner parts in which the connection parts and the band parts are contiguous. A thickness of each of the external electrodes may be 50 nm to 2 ?m. The external electrodes may be formed using a barrel-type sputtering method. A ratio t2/t1 may satisfy 0.7 to 1.2, where t1 is a thickness of each connection part and t2 is a thickness of each band part. A ratio t3/t1 may satisfy 0.7 to 1.0, where t3 is a thickness of each corner part.

Abstract: A semiconductor device includes an insulating layer on a substrate; a via extending from within the substrate and extending through one face of the substrate and a bottom face of a trench defined in the insulating layer such that a portion of a sidewall and a top face of the via are exposed through the substrate; and a pad contacting the exposed portion of the sidewall and the top face of the via. The pad fills the trench. The insulating layer includes a passivation layer on the substrate, and a protective layer is on the passivation layer. An etch stop layer is absent between the passivation layer and the protective layer. A vertical level of a bottom face of the trench is higher than a vertical level of one face of the substrate and is lower than a vertical level of a top face of the passivation layer.

Abstract: A multilayer ceramic capacitor includes a body having a dielectric layer and internal electrodes disposed to be alternately exposed to the third and fourth surfaces with the dielectric layer interposed therebetween. External electrodes include connection parts respectively formed on opposing surfaces of the body, band parts formed to extend from the connection parts to portions of side surfaces of the body, and corner parts in which the connection parts and the band parts are contiguous. A thickness of each of the external electrodes may be 50 nm to 2 ?m. The external electrodes may be formed using a barrel-type sputtering method. A ratio t2/t1 may satisfy 0.7 to 1.2, where t1 is a thickness of each connection part and t2 is a thickness of each band part. A ratio t3/t1 may satisfy 0.7 to 1.0, where t3 is a thickness of each corner part.

Abstract: A multilayer ceramic capacitor includes a body having a dielectric layer and internal electrodes disposed to be alternately exposed to the third and fourth surfaces with the dielectric layer interposed therebetween. External electrodes include connection parts respectively formed on opposing surfaces of the body, band parts formed to extend from the connection parts to portions of side surfaces of the body, and corner parts in which the connection parts and the band parts are contiguous. A thickness of each of the external electrodes may be 50 nm to 2 ?m. The external electrodes may be formed using a barrel-type sputtering method. A ratio t2/t1 may satisfy 0.7 to 1.2, where t1 is a thickness of each connection part and t2 is a thickness of each band part. A ratio t3/t1 may satisfy 0.7 to 1.0, where t3 is a thickness of each corner part.

Abstract: A multilayer ceramic capacitor includes a body having a dielectric layer and internal electrodes disposed to be alternately exposed to the third and fourth surfaces with the dielectric layer interposed therebetween. External electrodes include connection parts respectively formed on opposing surfaces of the body, band parts formed to extend from the connection parts to portions of side surfaces of the body, and corner parts in which the connection parts and the band parts are contiguous. A thickness of each of the external electrodes may be 50 nm to 2 ?m. The external electrodes may be formed using a barrel-type sputtering method. A ratio t2/t1 may satisfy 0.7 to 1.2, where t1 is a thickness of each connection part and t2 is a thickness of each band part. A ratio t3/t1 may satisfy 0.7 to 1.0, where t3 is a thickness of each corner part.

Abstract: A multilayer electronic component includes: a capacitor body including first and second internal electrodes disposed to be alternately exposed through opposite surfaces, respectively, with respective dielectric layers interposed therebetween; first and second thin film layers including at least one of titanium nitride (TiN), ruthenium (Ru), platinum (Pt), iridium (Ir), or titanium (Ti), disposed on the surfaces of the capacitor body, and connected to the first and second internal electrodes, respectively; and first and second external electrodes formed on the first and second thin film layers. A thickness of the first or second thin film layer is less than or equal to 60 nm.

Abstract: A semiconductor package includes a frame having a first through-hole, a semiconductor chip disposed on the first through-hole an having an active surface on which a connection pad is disposed and an inactive surface, a first encapsulant covering at least a portion of the inactive surface and a side surface of the semiconductor chip, a connection structure disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad of the semiconductor chip and a ground pattern layer, a side surface cover layer covering at least an outer side surface of the frame, and a metal layer disposed on the upper surface of the first encapsulant and extending downwardly along the side surface cover layer to cover the side surface cover layer and a portion of the side surface of the connection structure.

Abstract: A multilayer electronic component for enhancing damp proof reliability includes: a capacitor body including a plurality of dielectric layers, and first and second internal electrodes, alternately disposed across the dielectric layers to expose one end of the first and second electrodes through third and fourth surfaces of the capacitor body; first and second conductive layers disposed on the third and fourth surfaces of the capacitor body and connected to the first and second internal electrodes, respectively; first and second plating layers covering surfaces of the first and second conductive layers; and a plurality of coating layers configured in a multilayer structure on a surface of the capacitor body to expose the first and second plating layers and having an entire thickness of 10 nm to 200 nm.

Abstract: A multilayer ceramic capacitor includes a body including a dielectric layer and internal electrodes with external electrodes disposed on one surface of the body, wherein the external electrodes include a first electrode layer disposed on one surface of the body, in contact with the internal electrodes, and including titanium nitride (TiN), and a second electrode layer disposed on the first electrode layer.

Abstract: A semiconductor package includes a frame having a first through-hole, a semiconductor chip disposed on the first through-hole an having an active surface on which a connection pad is disposed and an inactive surface, a first encapsulant covering at least a portion of the inactive surface and a side surface of the semiconductor chip, a connection structure disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad of the semiconductor chip and a ground pattern layer, a side surface cover layer covering at least an outer side surface of the frame, and a metal layer disposed on the upper surface of the first encapsulant and extending downwardly along the side surface cover layer to cover the side surface cover layer and a portion of the side surface of the connection structure.

Abstract: A semiconductor package includes a frame having a first through-hole, a semiconductor chip disposed on the first through-hole an having an active surface on which a connection pad is disposed and an inactive surface, a first encapsulant covering at least a portion of the inactive surface and a side surface of the semiconductor chip, a connection structure disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad of the semiconductor chip and a ground pattern layer, a side surface cover layer covering at least an outer side surface of the frame, and a metal layer disposed on the upper surface of the first encapsulant and extending downwardly along the side surface cover layer to cover the side surface cover layer and a portion of the side surface of the connection structure.

Abstract: A semiconductor package includes a frame having a first through-hole, a semiconductor chip disposed on the first through-hole an having an active surface on which a connection pad is disposed and an inactive surface, a first encapsulant covering at least a portion of the inactive surface and a side surface of the semiconductor chip, a connection structure disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad of the semiconductor chip and a ground pattern layer, a side surface cover layer covering at least an outer side surface of the frame, and a metal layer disposed on the upper surface of the first encapsulant and extending downwardly along the side surface cover layer to cover the side surface cover layer and a portion of the side surface of the connection structure.

Abstract: A thin film capacitor includes a body including a lower electrode formed on a substrate, a plurality of first electrode layers, and a plurality of second electrode layers stacked alternately with the plurality of first electrode layers, with one of the dielectric layers interposed therebetween. The lower electrode and the first electrode layer have the same polarity as each other, and surface roughness of the first and second electrode layers is less than that of the dielectric layers, thereby securing capacitance and characteristics of the dielectric layers.

Abstract: A thin film capacitor includes a capacitor body formed by alternately stacking first and second electrode layers and a dielectric layer on a substrate, and having the second electrode layer disposed in an uppermost portion thereof, and a stress alleviation layer formed on the uppermost second electrode layer. The stress alleviation layer is formed of a material having a coefficient of thermal expansion higher than those of the substrate and the dielectric layer.

Abstract: A thin-film capacitor includes a body having a plurality of dielectric layers and first and second electrode layers alternately stacked on a substrate, first and second electrode pads disposed on one surface of the body, a plurality of vias having a multistage shape being disposed in the body, a first via of the plurality of vias connects the first electrode layer to the first electrode pad, and penetrates from the surface of the body to a first lowermost electrode layer adjacent the substrate, a second via of the plurality of vias connects the second electrode layer to the second electrode pad, and penetrates from the surface of the body to a second lowermost electrode layer adjacent the substrate and an upper surface of the first electrode layer is exposed in the first via, and an upper surface of the second electrode layer is exposed in the second via.

Abstract: A piezoelectric oscillator, and method of making the same, includes an oscillation substrate comprising an oscillating part and a surrounding part, wherein the surrounding part is thinner than the oscillating part, and oscillating electrodes disposed on an upper surface and a lower surface of the oscillating part. The oscillation substrate is configured according to H=400.59×S+1.75±1.5, wherein H=100×(T2/T1) and S=T2/(L1?L2), wherein L1 represents an entire length of the oscillation substrate, L2 represents a length of the oscillating part, T1 represents a thickness of the oscillating part, and T2 represents a step height between the oscillating part and the surrounding part.

Abstract: A multilayer ceramic capacitor includes a body including a dielectric layer and internal electrodes with external electrodes disposed on one surface of the body, wherein the external electrodes include a first electrode layer disposed on one surface of the body, in contact with the internal electrodes, and including titanium nitride (TiN), and a second electrode layer disposed on the first electrode layer.

Abstract: A multilayer electronic component includes: a capacitor body including first and second internal electrodes disposed to be alternately exposed through opposite surfaces, respectively, with respective dielectric layers interposed therebetween; first and second thin film layers including at least one of titanium nitride (TiN), ruthenium (Ru), platinum (Pt), iridium (Ir), or titanium (Ti), disposed on the surfaces of the capacitor body, and connected to the first and second internal electrodes, respectively; and first and second external electrodes formed on the first and second thin film layers. A thickness of the first or second thin film layer is less than or equal to 60 nm.

Abstract: A multilayer electronic component for enhancing damp proof reliability includes: a capacitor body including a plurality of dielectric layers, and first and second internal electrodes, alternately disposed across the dielectric layers to expose one end of the first and second electrodes through third and fourth surfaces of the capacitor body; first and second conductive layers disposed on the third and fourth surfaces of the capacitor body and connected to the first and second internal electrodes, respectively; first and second plating layers covering surfaces of the first and second conductive layers; and a plurality of coating layers configured in a multilayer structure on a surface of the capacitor body to expose the first and second plating layers and having an entire thickness of 10 nm to 200 nm.