Abstract: A method for fabricating an array substrate, an array substrate and a display device are provided. The method for fabricating the array substrate includes: forming a spacer layer on the array substrate, the spacer layer is disposed under a planarized layer and corresponds to a location of a via hole in the planarized layer, wherein the planarized layer is formed of a hot melt material.

Abstract: The method for manufacturing the TFT includes: forming a semiconductor film, a doped semiconductor film, a source/drain electrode film, and a first patterned photoresist layer sequentially; performing first etching to remove the source/drain electrode film on a region that is not covered by the first patterned photoresist layer; performing second etching to remove the doped semiconductor film and the semiconductor film on a region that is not covered by the first patterned photoresist layer; performing ashing treatment on the photoresist layer to remove the photoresist layer on the channel region; hard-baking the photoresist layer after the ashing treatment; performing third etching to remove the source/drain electrode film on a region that is not covered by the photoresist layer; and performing fourth etching to remove the doped semiconductor film on the region that is not covered by the photoresist layer.

Abstract: A method for fabricating an array substrate, an array substrate and a display device are provided. The method for fabricating the array substrate includes: forming a spacer layer on the array substrate, the spacer layer is disposed under a planarized layer and corresponds to a location of a via hole in the planarized layer, wherein the planarized layer is formed of a hot melt material.

Abstract: The method for manufacturing the TFT includes: forming a semiconductor film, a doped semiconductor film, a source/drain electrode film, and a first patterned photoresist layer sequentially; performing first etching to remove the source/drain electrode film on a region that is not covered by the first patterned photoresist layer; performing second etching to remove the doped semiconductor film and the semiconductor film on a region that is not covered by the first patterned photoresist layer; performing ashing treatment on the photoresist layer to remove the photoresist layer on the channel region; hard-baking the photoresist layer after the ashing treatment; performing third etching to remove the source/drain electrode film on a region that is not covered by the photoresist layer; and performing fourth etching to remove the doped semiconductor film on the region that is not covered by the photoresist layer.