Patents by Inventor Dong Kwan Kim

Dong Kwan Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240149837
    Abstract: A sensor cleaning apparatus for a vehicle includes: a sensor housing in which a driver and a sensor are mounted, a cover part configured to rotate and exposed to the outside of the sensor housing through an open region formed on a front surface of the sensor housing, and a blade part connected to the cover part. The blade is rotated as the driver is driven and provided to allow air generated by its rotation to flow toward a front surface and a rear surface of the cover.
    Type: Application
    Filed: June 13, 2023
    Publication date: May 9, 2024
    Applicants: HYUNDAI MOTOR COMPANY, KIA CORPORATION, DY AUTO Corporation
    Inventors: Sang Heon Wang, Nak Kyoung Kong, Dong Eun Cha, Kyung Hwan Kim, Jung Kwan Choi
  • Patent number: 11978146
    Abstract: The present invention relates to a three-dimensional reconstructing method of a 2D medical image. A three-dimensional reconstructing device includes: a communicator for receiving sequential 2D images with an arbitrary slice gap; a sliced image generator for generating at least one sliced image positioned between the 2D images based on a feature point of the adjacent 2D images; and a controller for reconstructing the 2D image into a 3D image by use of the generated sliced image and providing the 3D image.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: May 7, 2024
    Assignee: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Dong Young Lee, Yu Kyeong Kim, Jae Sung Lee, Min Soo Byun, Seong A Shin, Seung Kwan Kang
  • Patent number: 11894403
    Abstract: A semiconductor package including a semiconductor chip on a package substrate, a transparent substrate on the semiconductor chip, an attachment dam between the semiconductor chip and the transparent substrate, the attachment dam extending along an edge of the semiconductor chip, a first molding layer on the package substrate and surrounding a side surface of the semiconductor chip and including a first epoxy resin, and a second molding layer on the package substrate and filling a space between the semiconductor chip and the first molding layer and including a second epoxy resin. The first epoxy resin includes a first filler containing at least one of silica or alumina. The second epoxy resin includes a second filler containing at least one of silica or alumina. The content of the second filler in the second epoxy resin is greater than a content of the first filler in the first epoxy resin.
    Type: Grant
    Filed: April 25, 2021
    Date of Patent: February 6, 2024
    Inventor: Dong Kwan Kim
  • Publication number: 20230298309
    Abstract: There is provided a multi-scale object detection device. The device includes an image frame acquisition unit for acquiring a plurality of consecutive image frames, a critical region extractor for extracting at least one second critical region from a current image frame based on at least one first critical region extracted from a previous image frame among the consecutive image frames, a multi-scale object detector whose operation involves a first object detection process for the current image frame and a second object detection process for the at least one second critical region, and an object detection integration unit for integrating the results of the first and second object detection processes.
    Type: Application
    Filed: December 29, 2022
    Publication date: September 21, 2023
    Applicant: University Industry Foundation, Yonsei University
    Inventors: Han Jun KIM, Seon Yeong HEO, Dong Kwan KIM
  • Publication number: 20220324046
    Abstract: The present invention relates to a method for manufacturing a core plug of a gas turbine vane, and more particularly to plan and design a core plug formation using brazing comprising: a first step of designing and planning a formation of a core plug; a second step of cutting a Hastelloy X plate according to the design of the core plug; a third step of fabricating a preform of the core plug; a fourth step of spot-welding a trailing edge; a fifth step of pasting a brazing filler; a sixth step of performing brazing heat treatment; a seventh step of performing grinding a brazed portion; an eighth step of performing a grit blasting. According to the method for manufacturing a core plug of a gas turbine vane using brazing of the present invention above-mentioned, there is a significant effect of reducing manufacturing cost by in which the process is simple, and there is no deformation, shrinkages, cracks, and the like, in contrast with a conventional welding method.
    Type: Application
    Filed: February 15, 2022
    Publication date: October 13, 2022
    Inventors: Hyun Ki KANG, Seok Yeong KANG, Sang Woo JO, Dong Kwan KIM, Young Ill AHN, Yun Jin KIM, Ha Yun SUNG
  • Publication number: 20220257116
    Abstract: The present invention relates to a fundus imaging device having an automatic focusing function, by which even a user, who is not a skilled expert, may easily photograph a fundus image, and interpret and analyze the photographed image to predict a degree of risk, the fundus imaging device controlling a focusing unit to adjust a focus of a pupil image received from a pupil imaging unit, and controlling a fundus imaging unit to photograph a fundus image when the pupil image is in focus.
    Type: Application
    Filed: July 29, 2020
    Publication date: August 18, 2022
    Applicant: UMI OPTICS
    Inventor: Dong-Kwan KIM
  • Publication number: 20220085086
    Abstract: A semiconductor package comprises a package substrate, a semiconductor chip mounted on the package substrate, a transparent substrate disposed on the semiconductor chip, an attachment dam between the semiconductor chip and the transparent substrate, the attachment dam extending along an edge of the semiconductor chip to define a gap between the semiconductor chip and the transparent substrate, a first molding layer on the package substrate, the first molding layer surrounding a side surface of the semiconductor chip and including a first epoxy resin composition, and a second molding layer on the package substrate, the second molding layer filling a space between the semiconductor chip and the first molding layer and including a second epoxy resin composition, wherein the first epoxy resin composition includes a first filler containing at least one of silica or alumina, the second epoxy resin composition includes a second filler containing at least one of silica or alumina, and a content of the second filler w
    Type: Application
    Filed: April 25, 2021
    Publication date: March 17, 2022
    Inventor: DONG KWAN KIM
  • Publication number: 20210280562
    Abstract: A method of manufacturing a semiconductor package includes forming a first redistribution structure, forming a plurality of conductive pillars on the first redistribution structure, mounting the first semiconductor chip on the first redistribution structure, forming an encapsulant configured to cover an upper surface of the first redistribution structure, the plurality of conductive pillars, and the first semiconductor chip, planarizing the encapsulant, exposing the plurality of conductive pillars by forming an opening in the planarized encapsulant, and forming a second redistribution structure connected to the plurality of conductive pillars on the first semiconductor chip and the encapsulant. Upper surfaces of the plurality of conductive pillars are located at a lower level than the upper surface of the first semiconductor chip, and an upper surface of a connection via included in the second redistribution structure has a width greater than a width of a lower surface of the connection via.
    Type: Application
    Filed: May 10, 2021
    Publication date: September 9, 2021
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kun Sil LEE, Dong Kwan KIM
  • Patent number: 11031375
    Abstract: A method of manufacturing a semiconductor package includes forming a first redistribution structure, forming a plurality of conductive pillars on the first redistribution structure, mounting the first semiconductor chip on the first redistribution structure, forming an encapsulant configured to cover an upper surface of the first redistribution structure, the plurality of conductive pillars, and the first semiconductor chip, planarizing the encapsulant, exposing the plurality of conductive pillars by forming an opening in the planarized encapsulant, and forming a second redistribution structure connected to the plurality of conductive pillars on the first semiconductor chip and the encapsulant. Upper surfaces of the plurality of conductive pillars are located at a lower level than the upper surface of the first semiconductor chip, and an upper surface of a connection via included in the second redistribution structure has a width greater than a width of a lower surface of the connection via.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kun Sil Lee, Dong Kwan Kim
  • Patent number: 10896879
    Abstract: A semiconductor package includes a semiconductor package substrate. An insulating layer is disposed on the semiconductor package substrate. A semiconductor chip is disposed on the semiconductor package substrate and is covered by the insulating layer. A reflective layer is disposed on the insulating layer and is spaced apart from the semiconductor chip. The reflective layer is configured to selectively transmit radiation through to the insulating layer. A protective layer is disposed on the reflective layer.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: January 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kun Sil Lee, Dong Kwan Kim, Bo Ram Kang, Ho Geon Song, Won Keun Kim
  • Patent number: 10879225
    Abstract: A semiconductor package includes a package substrate, a first semiconductor device arranged on the package substrate, at least one second semiconductor device on the first semiconductor device to partially cover the first semiconductor device from a top down view, a heat dissipating insulation layer coated on the first semiconductor device and the at least one second semiconductor device, a conductive heat dissipation structure arranged on the heat dissipating insulation layer on a portion of the first semiconductor device not covered by the second semiconductor device, and a molding layer on the package substrate to cover the first semiconductor device and the at least one second semiconductor device. The heat dissipating insulation layer is formed of an electrically insulating and thermally conductive material, and the conductive heat dissipation structure formed of an electrically and thermally conductive material.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: December 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won-Keun Kim, Kyung-Suk Oh, Hwa-Il Jin, Dong-Kwan Kim, Yeong-Seok Kim, Jae-Choon Kim, Seung-Tae Hwang
  • Patent number: 10847473
    Abstract: A semiconductor package can include a substrate and a semiconductor chip on the substrate. A first molding portion can cover the semiconductor chip and can include a first sidewall and a second sidewall opposite each other. A second molding portion can extend on the substrate along the first sidewall and along the second sidewall, where the first molding portion can include a nonconductive material, and the second molding portion can include a conductive material.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Han Ko, Bo Ram Kang, Dong Kwan Kim
  • Publication number: 20200185352
    Abstract: A method of manufacturing a semiconductor package includes forming a first redistribution structure, forming a plurality of conductive pillars on the first redistribution structure, mounting the first semiconductor chip on the first redistribution structure, forming an encapsulant configured to cover an upper surface of the first redistribution structure, the plurality of conductive pillars, and the first semiconductor chip, planarizing the encapsulant, exposing the plurality of conductive pillars by forming an opening in the planarized encapsulant, and forming a second redistribution structure connected to the plurality of conductive pillars on the first semiconductor chip and the encapsulant. Upper surfaces of the plurality of conductive pillars are located at a lower level than the upper surface of the first semiconductor chip, and an upper surface of a connection via included in the second redistribution structure has a width greater than a width of a lower surface of the connection via.
    Type: Application
    Filed: May 17, 2019
    Publication date: June 11, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kun Sil LEE, Dong Kwan KIM
  • Publication number: 20200135710
    Abstract: A semiconductor package includes a package substrate, a first semiconductor device arranged on the package substrate, at least one second semiconductor device on the first semiconductor device to partially cover the first semiconductor device from a top down view, a heat dissipating insulation layer coated on the first semiconductor device and the at least one second semiconductor device, a conductive heat dissipation structure arranged on the heat dissipating insulation layer on a portion of the first semiconductor device not covered by the second semiconductor device, and a molding layer on the package substrate to cover the first semiconductor device and the at least one second semiconductor device. The heat dissipating insulation layer is formed of an electrically insulating and thermally conductive material, and the conductive heat dissipation structure formed of an electrically and thermally conductive material.
    Type: Application
    Filed: June 4, 2019
    Publication date: April 30, 2020
    Inventors: Won-Keun KIM, Kyung-Suk OH, Hwa-Il JIN, Dong-Kwan KIM, Yeong-Seok KIM, Jae-Choon KIM, Seung-Tae HWANG
  • Patent number: 10590217
    Abstract: Provided are a curable compound, a photoinitiator, and a curable resin composition comprising at least two types of thermal initiators, each having different initiation reaction temperature. Since the curable resin composition can improve a curing rate while having a high conversion rate, the curable resin composition is suitable for manufacturing thick films.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 17, 2020
    Assignee: LG HAUSYS, LTD.
    Inventors: Dong Kwan Kim, Min Hee Lee
  • Publication number: 20190287920
    Abstract: A semiconductor package includes a semiconductor package substrate. An insulating layer is disposed on the semiconductor package substrate. A semiconductor chip is disposed on the semiconductor package substrate and is covered by the insulating layer. A reflective layer is disposed on the insulating layer and is spaced apart from the semiconductor chip. The reflective layer is configured to selectively transmit radiation through to the insulating layer. A protective layer is disposed on the reflective layer.
    Type: Application
    Filed: November 27, 2018
    Publication date: September 19, 2019
    Inventors: KUN SIL LEE, DONG KWAN KIM, BO RAM KANG, HO GEON SONG, WON KEUN KIM
  • Publication number: 20190122995
    Abstract: A semiconductor package can include a substrate and a semiconductor chip on the substrate. A first molding portion can cover the semiconductor chip and can include a first sidewall and a second sidewall opposite each other. A second molding portion can extend on the substrate along the first sidewall and along the second sidewall, where the first molding portion can include a nonconductive material, and the second molding portion can include a conductive material.
    Type: Application
    Filed: August 1, 2018
    Publication date: April 25, 2019
    Inventors: Ji-Han Ko, Bo Ram Kang, Dong Kwan Kim
  • Patent number: 10004105
    Abstract: Provided is a network self-healing method in which, when a link between a parent device and a child device breaks down in a wireless communication network of a cluster-tree structure in which a main communication device (referred to an access point (AP)) manages network operation, routers that are devices capable of having their child devices, and end devices that are devices incapable of having their child devices are associated with each other in a parent-child device relationship, the link is restored. When a router becomes an orphan device, the router makes network re-association in a cluster unit while maintaining synchronized operation with its child devices, and thus time, energy and signaling burden for network self-healing is largely reduced.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: June 19, 2018
    Assignee: Seoul National University R&DB Foundation
    Inventors: Yong Hwan Lee, Jin Seok Han, Jae Seok Bang, Dong Kwan Kim
  • Patent number: 9826901
    Abstract: The present invention relates to an adaptor for a slit lamp microscope. According to one embodiment of the present invention, the invention provides the advantages of: facilitating the maintenance/repair of a slit lamp microscope since a camera member used for the slit lamp microscope is simply attached or detached; simply and easily inspecting and photographing a subject's eye; and obtaining a high-resolution video or image for the subject's eye at low costs.
    Type: Grant
    Filed: February 3, 2015
    Date of Patent: November 28, 2017
    Inventors: Dong Kwan Kim, Dong Sik Kim
  • Patent number: 9718132
    Abstract: Provided is a manufacturing method of uniformly spherical gold nanoparticles using a synthesis method for controlling a size and a shape by repeating an etching and growing.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: August 1, 2017
    Assignees: Korea Basic Science Institute, Research & Business Foundation SUNGKYUNKWAN UNIVERSITY
    Inventors: Gaehang Lee, Gi-Ra Yi, You-Jin Lee, Dong Kwan Kim