Patents by Inventor Dong-kyun Nam

Dong-kyun Nam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11925726
    Abstract: The present disclosure is related to a perfusable-type bio-dual proximal tubule cell construct and a producing method thereof capable of applying an in vitro artificial organ model configured to include a first bioink comprising a decellularized substance derived from a mammalian kidney tissue and human umbilical vascular endothelial cells (HUVECs) and a second bioink comprising the decellularized substance and renal proximal tubular epithelial cells (RPTECs), wherein the first bioink and the second bioink are coaxial and printed in tubular constructs having different inner diameters. According to the present disclosure, it is possible to use the renal proximal tubule-on-a-chip as a bioreactor capable of observing a biological drug reaction similar to a real drug by perfusing various drugs to the renal proximal tubule-on-a-chip.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: March 12, 2024
    Assignees: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION, THE CATHOLIC UNIVERSITY OF KOREA INDUSTRY—ACADEMIC COOPERATION FOUNDATION
    Inventors: Dong-Woo Cho, Wonil Han, Narendra K. Singh, Yong Kyun Kim, Sun Ah Nam
  • Patent number: 10877312
    Abstract: Provided is a reflection system including a windshield and a feeder. The windshield includes an upper transparent layer, an upper electrode, a liquid crystal layer, a lower electrode array, and a lower transparent layer, and the feeder is configured to apply a voltage pattern to the lower electrode array. A refractive index of the liquid crystal layer varies across the liquid crystal layer according to the voltage pattern applied by the feeder to the lower electrode array, and the feeder is configured to apply a first voltage pattern to cause a first change in the refractive index of the liquid crystal layer such that parallel light rays incident to the windshield and reflected from the upper transparent layer and the lower transparent layer, respectively, meet at a virtual focal point.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: December 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoonsun Choi, Dong Kyun Nam, Jinho Lee
  • Publication number: 20200192156
    Abstract: Provided is a reflection system including a windshield and a feeder. The windshield includes an upper transparent layer, an upper electrode, a liquid crystal layer, a lower electrode array, and a lower transparent layer, and the feeder is configured to apply a voltage pattern to the lower electrode array. A refractive index of the liquid crystal layer varies across the liquid crystal layer according to the voltage pattern applied by the feeder to the lower electrode array, and the feeder is configured to apply a first voltage pattern to cause a first change in the refractive index of the liquid crystal layer such that parallel light rays incident to the windshield and reflected from the upper transparent layer and the lower transparent layer, respectively, meet at a virtual focal point.
    Type: Application
    Filed: May 24, 2019
    Publication date: June 18, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yoonsun Choi, Dong Kyun Nam, Jinho Lee
  • Patent number: 7704892
    Abstract: A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor substrate, the isolation layer, and a gate pattern. An etch stopper pattern having at least one layer for preventing the etching of the isolation layer is formed under the local interconnection layer. The etch stopper pattern having at least one layer for preventing the etching of the isolation layer can be included when forming the local interconnection layer, thereby preventing leakage current caused by the etching of the isolation layer, improving the electrical characteristics of a semiconductor device, and improving the yield of a process of manufacturing a semiconductor device.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: April 27, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-kyun Nam, Heon-jong Shin, Hyung-tae Ji
  • Patent number: 7476598
    Abstract: A photodiode and a method of manufacturing the photodiode are provided. The method includes forming a diode junction structure including a light receiving unit and an electrode unit on a semiconductor substrate, forming a buffer oxide layer and an etching blocking layer on the junction structure, forming an interlayer insulating layer and an intermetal insulating layer and an interconnecting structure, exposing the etching blocking layer by etching the intermetal insulating layer and the interlayer insulating layer, removing a portion of the etching blocking layer and the buffer oxide layer of the light-receiving unit by dry etching, and exposing a semiconductor surface of the light-receiving unit by wet etching.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: January 13, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Sung Son, Sung-Ryoul Bae, Dong-Kyun Nam
  • Publication number: 20090008739
    Abstract: Methods of manufacturing a photo diode include sequentially forming a buried layer of a first conductivity type, a first epitaxial layer of the first conductivity type, and a second epitaxial layer of a second conductivity type on a substrate. The second and first epitaxial layers are etched to form a trench that exposes a portion of the buried layer. A conductive plug of the first conductivity type is formed in the trench. A first electrode is formed on an upper surface of the second epitaxial layer. A second electrode may be formed to contact an upper surface of the conductive plug. Photodiodes having a conductive plug contact to a buried layer are also provided.
    Type: Application
    Filed: September 17, 2008
    Publication date: January 8, 2009
    Inventors: Sung-ryoul Bae, Dong-kyun Nam
  • Patent number: 7465638
    Abstract: There is provided a bipolar transistor (with a respective fabrication method) that provides superior noise characteristics and gain diffusion. The fabricating method includes forming a first base region at a collector region, which in turn is formed on a substrate. A first silicon layer is formed on the base region, and a second silicon layer is formed on the first silicon layer using a forming method different from the method used in forming the first silicon layer. An emitter region is then formed from impurities at the base region by performing a thermal process.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: December 16, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kye-Won Maeng, Sung-Ryoul Bae, Dong-Kyun Nam, Tae-Jin Kim
  • Patent number: 7427530
    Abstract: Methods of manufacturing a photo diode include sequentially forming a buried layer of a first conductivity type, a first epitaxial layer of the first conductivity type, and a second epitaxial layer of a second conductivity type on a substrate. The second and first epitaxial layers are etched to form a trench that exposes a portion of the buried layer. A conductive plug of the first conductivity type is formed in the trench. A first electrode is formed on an upper surface of the second epitaxial layer. A second electrode may be formed to contact an upper surface of the conductive plug. Photodiodes having a conductive plug contact to a buried layer are also provided.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: September 23, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-ryoul Bae, Dong-kyun Nam
  • Publication number: 20070243656
    Abstract: A photodiode and a method of manufacturing the photodiode are provided. The method includes forming a diode junction structure including a light receiving unit and an electrode unit on a semiconductor substrate, forming a buffer oxide layer and an etching blocking layer on the junction structure, forming an interlayer insulating layer and an intermetal insulating layer and an interconnecting structure, exposing the etching blocking layer by etching the intermetal insulating layer and the interlayer insulating layer, removing a portion of the etching blocking layer and the buffer oxide layer of the light-receiving unit by dry etching, and exposing a semiconductor surface of the light-receiving unit by wet etching.
    Type: Application
    Filed: February 2, 2007
    Publication date: October 18, 2007
    Inventors: Ho-Sung Son, Sung-Ryoul Bae, Dong-Kyun Nam
  • Patent number: 7190012
    Abstract: A photodiode and a method of manufacturing the photodiode are provided. The method includes forming a diode junction structure including a light receiving unit and an electrode unit on a semiconductor substrate, forming a buffer oxide layer and an etching blocking layer on the junction structure, forming an interlayer insulating layer and an intermetal insulating layer and an interconnecting structure, exposing the etching blocking layer by etching the intermetal insulating layer and the interlayer insulating layer, removing a portion of the etching blocking layer and the buffer oxide layer of the light-receiving unit by dry etching, and exposing a semiconductor surface of the light-receiving unit by wet etching.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: March 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Sung Son, Sung-Ryoul Bae, Dong-Kyun Nam
  • Publication number: 20070010090
    Abstract: A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor substrate, the isolation layer, and a gate pattern. An etch stopper pattern having at least one layer for preventing the etching of the isolation layer is formed under the local interconnection layer. The etch stopper pattern having at least one layer for preventing the etching of the isolation layer can be included when forming the local interconnection layer, thereby preventing leakage current caused by the etching of the isolation layer, improving the electrical characteristics of a semiconductor device, and improving the yield of a process of manufacturing a semiconductor device.
    Type: Application
    Filed: September 7, 2006
    Publication date: January 11, 2007
    Inventors: Dong-kyun Nam, Heon-jong Shin, Hyung tae Ji
  • Publication number: 20060252214
    Abstract: There is provided a bipolar transistor (with a respective fabrication method) that provides superior noise characteristics and gain diffusion. The fabricating method includes forming a first base region at a collector region, which in turn is formed on a substrate. A first silicon layer is formed on the base region, and a second silicon layer is formed on the first silicon layer using a forming method different from the method used in forming the first silicon layer. An emitter region is then formed from impurities at the base region by performing a thermal process.
    Type: Application
    Filed: April 27, 2006
    Publication date: November 9, 2006
    Inventors: Kye-Won Maeng, Sung-Ryoul Bae, Dong-Kyun Nam, Tae-Jin Kim
  • Patent number: 7122850
    Abstract: A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor substrate, the isolation layer, and a gate pattern. An etch stopper pattern having at least one layer for preventing the etching of the isolation layer is formed under the local interconnection layer. The etch stopper pattern having at least one layer for preventing the etching of the isolation layer can be included when forming the local interconnection layer, thereby preventing leakage current caused by the etching of the isolation layer, improving the electrical characteristics of a semiconductor device, and improving the yield of a process of manufacturing a semiconductor device.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: October 17, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-kyun Nam, Heon-jong Shin, Hyung-tae Ji
  • Patent number: 6930008
    Abstract: A method of fabricating a complementary bipolar junction transistor includes forming a polycrystalline silicon layer on an NPN bipolar junction transistor region and a PNP bipolar junction transistor region, respectively implanting an N-type impurity and a P-type impurity into the polycrystalline silicon layer, and then diffusing to respectively form an N-type emitter region and a P-type emitter region within a P-type base region and an N-type base region. By patterning the polycrystalline silicon layer, an N-type emitter electrode and a P-type emitter electrode are simultaneously formed. The polycrystalline silicon layer is used for simultaneously forming the N-type emitter electrode of the NPN bipolar junction transistor and the P-type emitter electrode of the PNP bipolar junction transistor by a single depositing and etching process.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: August 16, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-kyun Nam, Sung-ryoul Bae
  • Publication number: 20050148135
    Abstract: A method of fabricating a complementary bipolar junction transistor includes forming a polycrystalline silicon layer on an NPN bipolar junction transistor region and a PNP bipolar junction transistor region, respectively implanting an N-type impurity and a P-type impurity into the polycrystalline silicon layer, and then diffusing to respectively form an N-type emitter region and a P-type emitter region within a P-type base region and an N-type base region. By patterning the polycrystalline silicon layer, an N-type emitter electrode and a P-type emitter electrode are simultaneously formed. The polycrystalline silicon layer is used for simultaneously forming the N-type emitter electrode of the NPN bipolar junction transistor and the P-type emitter electrode of the PNP bipolar junction transistor by a single depositing and etching process.
    Type: Application
    Filed: December 30, 2004
    Publication date: July 7, 2005
    Inventors: Dong-kyun Nam, Sung-ryoul Bae
  • Publication number: 20050133838
    Abstract: A photodiode and a method of manufacturing the photodiode are provided. The method includes forming a diode junction structure including a light receiving unit and an electrode unit on a semiconductor substrate, forming a buffer oxide layer and an etching blocking layer on the junction structure, forming an interlayer insulating layer and an intermetal insulating layer and an interconnecting structure, exposing the etching blocking layer by etching the intermetal insulating layer and the interlayer insulating layer, removing a portion of the etching blocking layer and the buffer oxide layer of the light-receiving unit by dry etching, and exposing a semiconductor surface of the light-receiving unit by wet etching.
    Type: Application
    Filed: December 2, 2004
    Publication date: June 23, 2005
    Inventors: Ho-Sung Son, Sung-Ryoul Bae, Dong-Kyun Nam
  • Publication number: 20050101073
    Abstract: Methods of manufacturing a photo diode include sequentially forming a buried layer of a first conductivity type, a first epitaxial layer of the first conductivity type, and a second epitaxial layer of a second conductivity type on a substrate. The second and first epitaxial layers are etched to form a trench that exposes a portion of the buried layer. A conductive plug of the first conductivity type is formed in the trench. A first electrode is formed on an upper surface of the second epitaxial layer. A second electrode may be formed to contact an upper surface of the conductive plug. Photodiodes having a conductive plug contact to a buried layer are also provided.
    Type: Application
    Filed: September 29, 2004
    Publication date: May 12, 2005
    Inventors: Sung-ryoul Bae, Dong-kyun Nam
  • Patent number: 6731724
    Abstract: A voice-enabled user interface and method for enabling a user that is providing audio and vocal input to access data from telephone service systems that are only responsive to dual tone multi-frequency (“DTMF”) signals. A user access the voice-enabled user interface with a telephone device and provides input that is translated into a DTMF translation that can be recognized by DTMF telephone service system. A template of the voice-enabled user interface maps menu states, prompts, and acceptable inputs of the DTMF telephone service system. The template also monitors the current state of the telephone service system at all times. The invention also enables a user to jump from one menu state to another menu state of the telephone service system without having to enter input for each menu state between the first and the second menu states.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: May 4, 2004
    Assignee: Pumatech, Inc.
    Inventors: Darren L. Wesemann, Makani Mason, Jon Willesen, Tae-Deok Kweon, Dong-Kyun Nam
  • Publication number: 20030049936
    Abstract: A semiconductor device having a local interconnection layer and a method for manufacturing the same are provided. A local interconnection layer is formed in an interlayer dielectric (ILD) layer on an isolation layer and a junction layer, for covering a semiconductor substrate, the isolation layer, and a gate pattern. An etch stopper pattern having at least one layer for preventing the etching of the isolation layer is formed under the local interconnection layer. The etch stopper pattern having at least one layer for preventing the etching of the isolation layer can be included when forming the local interconnection layer, thereby preventing leakage current caused by the etching of the isolation layer, improving the electrical characteristics of a semiconductor device, and improving the yield of a process of manufacturing a semiconductor device.
    Type: Application
    Filed: August 30, 2002
    Publication date: March 13, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong-Kyun Nam, Heon-Jong Shin, Hyung-Tae Ji
  • Publication number: 20020097848
    Abstract: A voice-enabled user interface and method for enabling a user that is providing audio and vocal input to access data from telephone service systems that are only responsive to dual tone multi-frequency (“DTMF”) signals. A user access the voice-enabled user interface with a telephone device and provides input that is translated into a DTMF translation that can be recognized by DTMF telephone service system. A template of the voice-enabled user interface maps menu states, prompts, and acceptable inputs of the DTMF telephone service system. The template also monitors the current state of the telephone service system at all times. The invention also enables a user to jump from one menu state to another menu state of the telephone service system without having to enter input for each menu state between the first and the second menu states.
    Type: Application
    Filed: June 22, 2001
    Publication date: July 25, 2002
    Inventors: Darren L. Wesemann, Makani Mason, Jon Willesen, Tae-Deok Kweon, Dong-Kyun Nam