Abstract: An integrated device comprising a die portion that includes a plurality of pads and a plurality of under bump metallization interconnects coupled to the plurality of pads, where the plurality of under bump metallization interconnects comprises a first under bump metallization interconnect. The integrated device includes a plurality of pillar interconnects coupled to the plurality of under bump metallization interconnects, where the plurality of pillar interconnects includes a first pillar interconnect. The first pillar interconnect includes a first width that corresponds to a widest part of the first pillar interconnect, and a second width that corresponds to a part of the first pillar interconnect that is vertically farthest away from the first under bump metallization interconnect, wherein the second width is less than the first width.

Abstract: A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects at least partially located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the metallization portion; and an optical fiber coupled to the optical integrated device.

Abstract: A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects at least partially located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

Abstract: Disclosed are techniques for integrated circuit device. In an aspect, an integrated circuit device includes a metallization structure that includes a top metal layer structure; a passivation layer on the metallization structure; a bump structure disposed on the first bump line structure; and a first polymer protection layer. The passivation layer may include one or more first openings. The first bump line structure may include one or more first extended portions respectively extending toward the top metal layer structure through the one or more first openings. The bump structure may be electrically coupled to the first bump line structure. The first polymer protection layer may be on the passivation layer, on a portion of the first bump line structure, and in contact with a side surface of the first bump line structure.

Abstract: A semiconductor die having a die interconnect and a die level distribution (DLD) metallization layer having a metal line and a metal pad having a width greater than the width of the metal line to support a larger die interconnect for improved signal path conductivity between the die interconnect and the metal pad is disclosed. Related integrated circuit (IC) packages and fabrication methods are also disclosed. The die includes a semiconductor layer, a DLD metallization structure, and a back end of line (BEOL) interconnect structure between the semiconductor layer and the DLD metallization structure. The DLD metallization structure mechanically supports die interconnects for coupling the die to another device, such as a package substrate or another die, and redistributes signals (e.g., power, ground, information) between the die interconnects and the semiconductor layer through the BEOL interconnect structure.

Abstract: An integrated device comprising a die substrate; a die interconnection portion coupled to the die substrate, wherein the die interconnection portion comprises: at least one die dielectric layer; and a plurality of die interconnects, wherein the die interconnection portion comprises: an inner die interconnection portion; and a periphery die interconnection portion, wherein the periphery die interconnect portion is free of the plurality of die interconnects; a plurality of pad interconnects coupled to the die interconnection portion; a plurality of metallization interconnects coupled to the plurality of pad interconnects, wherein at least one metallization interconnect from the plurality of metallization interconnects, vertically overlaps with the periphery die interconnection portion, and a plurality of pillar interconnects coupled to the plurality of metallization interconnects.

Abstract: An integrated device comprising a die substrate; a die interconnection coupled to the die substrate; an encapsulation layer coupled to a side surface of the die substrate and a side surface of the die interconnection; a plurality of pad interconnects coupled to the die interconnection; and a plurality of metallization interconnects, wherein one or more metallization interconnects from the plurality of metallization interconnects is coupled to one or more pad interconnects from the plurality of pad interconnects.

Abstract: Aspects disclosed in the detailed description include a semiconductor die having a die level distribution (DLD) metallization structure including a metal pad and a short via coupled to the metal pad to a metal interconnect in the die for improved signal path conductivity. The DLD metallization structure includes an outer metallization layer comprising the metal interconnect, a first passivation layer adjacent to the outer metallization layer and a DLD metallization layer adjacent to the first passivation layer. The DLD metallization layer comprises a first surface adjacent to the first passivation layer and a metal pad. The DLD metallization structure includes a first via extending in the second direction orthogonal to the first direction, the first via coupling the metal pad and the metal interconnect, the first via having a first aspect ratio between 0.06-0.5, inclusively.

Abstract: A package comprising a substrate; a first integrated device coupled to the substrate through at least a first plurality of solder interconnects; a second integrated device coupled to the substrate through at least a second plurality of solder interconnects; and a bridge coupled to the substrate, wherein the bridge comprises a plurality of spring pads.

Abstract: A package comprising a base substrate; a first integrated device coupled to the base substrate through a bonding material; a second integrated device coupled to the base substrate through the bonding material; a fill material coupled to the base substrate, the first integrated device and the second integrated device; and a metallization portion coupled to the first integrated device and the second integrated device.

Abstract: A die includes a plurality of pillar bumps configured to electrically connect the die to a substrate. The plurality of pillar bumps includes at least one first pillar bump having a first total pillar bump height. The at least one first pillar bump includes a first pillar having a first pillar height and a first solder cap having a first solder cap height. The plurality of pillar bumps includes at least one second pillar bump having a second pillar height substantially equal to the first total pillar bump height. The at least one second pillar bump includes a second pillar having a second pillar height and a second solder cap having a second solder cap height. The second pillar height is greater than the first pillar height, and the second solder cap height is less than the first solder cap height.

Abstract: Disclosed is a semiconductor device. In an aspect, a semiconductor device includes: a first-tier passive device including a substrate portion, a passive device portion, and a metallization portion disposed in a stacked configuration; and one or more second-tier passive devices disposed over the first-tier passive device. Each one of the one or more second-tier passive devices includes: a substrate portion, a passive device portion, and a metallization portion disposed in a stacked configuration; and a set of through substrate vias (TSVs) passing through a corresponding substrate portion and electrically coupled to a corresponding metallization portion. The semiconductor device comprises a passive component including the passive device portion of the first-tier passive device electrically coupled to one or more passive device portions of the one or more second-tier passive devices through the metallization portions of the first-tier passive device and the one or more second-tier passive devices.

Abstract: An integrated device includes a die having a contact pad and a solder cap electrically connected to the contact pad by a multi-layer interconnect pillar. The multi-layer interconnect pillar includes a base reinforcement layer, a cap reinforcement layer, and one or more solder layers disposed between the base reinforcement layer and the cap reinforcement layer.

Abstract: Disclosed are techniques for integrated circuit device. In an aspect, an integrated circuit device includes a metallization structure that includes a top metal layer structure; a passivation layer on the metallization structure; a bump structure disposed on the first bump line structure; and a first polymer protection layer. The passivation layer may include one or more first openings. The first bump line structure may include one or more first extended portions respectively extending toward the top metal layer structure through the one or more first openings. The bump structure may be electrically coupled to the first bump line structure. The first polymer protection layer may be on the passivation layer, on a portion of the first bump line structure, and in contact with a side surface of the first bump line structure.

Abstract: Substrate employing core with cavity embedding reduced height electrical device(s), and related integrated circuit (IC) packages and fabrication methods are also disclosed. The cavity of the core (that has one or more core layers) of the substrate includes an embedded electrical device structure that an electrical device built upon another second component(s) to make the overall height of the electrical device structure compatible with the height of the cavity of the core. In this manner, the design criteria used to select thickness or height of the core for providing the desired stability in the substrate can be incompatible with the thickness or the height of the embedded electrical device.

Abstract: A thermal compression flip chip (TCFC) bump may be used for high performance products that benefit from a fine pitch. In one example, a new TCFC bump structure adds a metal pad underneath the TCFC copper pillar bump to cover the exposed aluminum bump pad. This new structure prevents the pad from corroding and reduces mechanical stress to the pad and underlying silicon dielectric layers enabling better quality and reliability and further bump size reduction. For example, a flip chip connection may include a substrate; a metal pad on a contact side of the substrate and a first passivation layer on the contact side of the substrate to protect the metal pad from corrosion.

Abstract: A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

Abstract: A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects at least partially located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

Abstract: A package that includes a first integrated device comprising a first plurality of interconnects; a plurality of solder interconnects coupled to the first plurality of interconnects; a second integrated device comprising a second plurality of interconnects, wherein the second integrated device is coupled to the first integrated device through the second plurality of interconnects, the plurality of solder interconnects and the first plurality of interconnects; a polymer layer located between the first integrated device and the second integrated device; and a plurality of spacer balls located between the first integrated device and the second integrated device.

Abstract: Circuit packages with a polymer layer around the bump interconnects have a reduced number of shorts between the bump interconnects and have reduced underfill delamination. The circuit package includes a first component coupled to a second component through a plurality of bump interconnects employed for passing logic signals, data signals, and/or power. The bump interconnects extend from a surface of the first component and are coupled to contact pads on an opposing surface of the second component. The side surfaces of the bump interconnects extend in a direction from the second component to the first. The circuit package includes the polymer layer disposed on the surface of the first component around the bump interconnects and on the side surfaces of the bump interconnects. The polymer layer reduces shorts between the side surfaces of adjacent bump interconnects and reduces delamination of an underfill disposed between the first and second components.