Abstract: Provided is a two-stage self-organizing optimized aggregation method and system for distributed resources of a virtual power plant.

Abstract: The embodiments of the present application provide a processing unit. The processing unit comprises: an instruction fetching unit configured for fusing instruction of vector configuration instruction and vector operation instruction that are adjacent in order to obtain fusion instruction; an instruction decoding unit configured to decode the fusion instruction to obtain first execution information and second execution information; a vector configuration unit configured to execute the vector configuration instruction according to the first execution information, modify vector control register, and bypass the value of the modified vector control register to the vector operation unit; the vector operation unit configured to execute the vector operation instruction according to the second execution information and the value of the modified vector control register.

Abstract: An instruction processing apparatus is disclosed and includes: an instruction cache, which maps data blocks in a memory based on a multi-way set-associative structure and includes a plurality of cache lines; and an access control unit, coupled between an instruction fetch unit and the instruction cache, and adapted to read the plurality of cache lines respectively by using a plurality of data channels, and select a hit cache line from the plurality of cache lines by using a plurality of selection channels, to obtain an instruction, where the access control unit includes a path prediction unit, where the path prediction unit obtains, based on a type of the instruction, path prediction information corresponding to an instruction address, and enables at least one data channel and/or at least one selection channel based on the path prediction information.

Abstract: An instruction processing device and an instruction processing method are provided.

Abstract: An instruction processing device and an instruction processing method are disclosed. The instruction processing device includes: an instruction boundary prediction unit including circuitry configured to acquire an instruction packet of a variable-length instruction set and to add instruction prediction information to a plurality of instruction meta-fields in the instruction packet; and an instruction pipeline structure comprising an instruction fetch unit including an instruction boundary determination unit including circuitry configured to determine instruction boundary information according to the instruction prediction information to obtain one or more instructions in the instruction packet.

Abstract: A processor comprises a trusted execution environment and a non-trusted execution environment. The processor further comprises a common resource accessible in both the trusted execution environment and the non-trusted execution environment and an instruction processing device including circuitry configured to fetch an instruction for decoding and execute the decoded instruction. The instruction processing device includes circuitry further configured to determine consistency between a current execution environment of the processor and a resource status in response to a result from instruction decoding indicating that instruction involves access to the common resource, and load content corresponding to the current execution environment into the common resource in response to a determination that the current execution environment is inconsistent with the resource status, wherein the resource status indicates an execution environment corresponding to content in the common resource.

Abstract: A processor core, a processor, an apparatus, and an instruction processing method are disclosed. The processor core includes: an instruction fetch unit, where the instruction fetch unit includes a speculative execution predictor and the speculative execution predictor compares a program counter of a memory access instruction with a table entry stored in the speculative execution predictor and marks the memory access instruction; a scheduler unit adapted to adjust a send order of marked memory access instructions and send the marked memory access instructions according to the send order; an execution unit adapted to execute the memory access instructions according to the send order. In the instruction fetch unit, a memory access instruction is marked according to a speculative execution prediction result. In the scheduler unit, a send order of memory access instructions is determined according to the marked memory access instruction and the memory access instructions are sent.

Abstract: A process of microcellular foam molding an article includes using a modifier to modify properties of amorphous PLA, pouring the modified amorphous PLA into a high pressure vessel, dissolving an SCF in the high pressure vessel to impregnate the modified amorphous PLA in the high pressure vessel which is configured to allow the SCF to effuse through, forming foamed pellets, conveying the foamed pellets to a mold in a second vessel filled with water or oil, heating the second vessel, and cooling the second vessel until a foamed article is finished in the mold.

Abstract: The present disclosure provides a chip transfer substrate, a chip transfer device and a chip transfer method. The chip transfer substrate includes a substrate, a plurality of bases spaced apart from each other on the substrate, the plurality of bases being configured to carry micro light emitting diodes (Micro LEDs) to be transferred and being movable on the substrate; and a plurality of distance adjusting components each arranged between two adjacent bases and configured to adjust a distance between the two adjacent bases.

Abstract: A process of making a sole includes mixing a foaming material with a nucleating agent to form a plurality of local blanks belonging to different portions of a sole wherein the local blanks belonging to different portions have different ratios of the nucleating agent; injection molding the local blanks to form a plurality of cold molds which are joined together along a horizontal direction to form a sole blank; sulfurizing the sole blank; and subjecting the sole blank to supercritical foaming to produce a finished sole.

Abstract: An instruction processing device and an instruction processing method are disclosed. The instruction processing device includes: an instruction boundary prediction unit including circuitry configured to acquire an instruction packet of a variable-length instruction set and to add instruction prediction information to a plurality of instruction meta-fields in the instruction packet; and an instruction pipeline structure comprising an instruction fetch unit including an instruction boundary determination unit including circuitry configured to determine instruction boundary information according to the instruction prediction information to obtain one or more instructions in the instruction packet.

Abstract: An instruction processing device and an instruction processing method are provided.

Abstract: An instruction processing apparatus is disclosed and includes: an instruction cache, which maps data blocks in a memory based on a multi-way set-associative structure and includes a plurality of cache lines; and an access control unit, coupled between an instruction fetch unit and the instruction cache, and adapted to read the plurality of cache lines respectively by using a plurality of data channels, and select a hit cache line from the plurality of cache lines by using a plurality of selection channels, to obtain an instruction, where the access control unit includes a path prediction unit, where the path prediction unit obtains, based on a type of the instruction, path prediction information corresponding to an instruction address, and enables at least one data channel and/or at least one selection channel based on the path prediction information.

Abstract: A processor core, a processor, an apparatus, and an instruction processing method are disclosed. The processor core includes: an instruction fetch unit, where the instruction fetch unit includes a speculative execution predictor and the speculative execution predictor compares a program counter of a memory access instruction with a table entry stored in the speculative execution predictor and marks the memory access instruction; a scheduler unit adapted to adjust a send order of marked memory access instructions and send the marked memory access instructions according to the send order; an execution unit adapted to execute the memory access instructions according to the send order. In the instruction fetch unit, a memory access instruction is marked according to a speculative execution prediction result. In the scheduler unit, a send order of memory access instructions is determined according to the marked memory access instruction and the memory access instructions are sent.

Abstract: A process of microcellular foam molding an article includes using a modifier to modify properties of amorphous PLA, pouring the modified amorphous PLA into a high pressure vessel, dissolving an SCF in the high pressure vessel to impregnate the modified amorphous PLA in the high pressure vessel which is configured to allow the SCF to effuse through, forming foamed pellets, conveying the foamed pellets to a mold in a second vessel filled with water or oil, heating the second vessel, and cooling the second vessel until a foamed article is finished in the mold.

Abstract: The present disclosure provides a chip transfer substrate, a chip transfer device and a chip transfer method. The chip transfer substrate includes a substrate, a plurality of bases spaced apart from each other on the substrate, the plurality of bases being configured to carry micro light emitting diodes (Micro LEDs) to be transferred and being movable on the substrate; and a plurality of distance adjusting components each arranged between two adjacent bases and configured to adjust a distance between the two adjacent bases.

Abstract: A processor comprises a trusted execution environment and a non-trusted execution environment. The processor further comprises a common resource accessible in both the trusted execution environment and the non-trusted execution environment and an instruction processing device including circuitry configured to fetch an instruction for decoding and execute the decoded instruction. The instruction processing device includes circuitry further configured to determine consistency between a current execution environment of the processor and a resource status in response to a result from instruction decoding indicating that instruction involves access to the common resource, and load content corresponding to the current execution environment into the common resource in response to a determination that the current execution environment is inconsistent with the resource status, wherein the resource status indicates an execution environment corresponding to content in the common resource.

Abstract: The embodiments of the application disclose a control device for a gate driving circuit, a display panel and a display device. The control device for a gate driving circuit provided in the embodiment comprises a level shifter and a control module electrically connected with an output of the level shifter. The control module is used for controlling an output signal of the level shifter to be a low level signal when each input clock signal for the level shifter is low.

Abstract: The embodiments of the application disclose a control device for a gate driving circuit, a display panel and a display device. The control device for a gate driving circuit provided in the embodiment comprises a level shifter and a control module electrically connected with an output of the level shifter. The control module is used for controlling an output signal of the level shifter to be a low level signal when each input clock signal for the level shifter is low.

Abstract: The present invention provides a hybrid Raman/EDFA optical amplifier that utilizes a first optical detector that generates a first electrical or electronic signal that is proportional the combined optical power of the signal light and the leaked pump laser light, a second optical detector that generates a second electrical or electronic signal that is proportional to the power of the pump laser light and an electronic subtraction circuit that receives the first and second electrical or electronic signals and generates a difference signal that is proportional to only to the optical power of the signal light and insensitive to the power of the Raman pump laser light. The difference signal is utilized by an EDFA control circuit to control and/or adjust the operation of the EDFA based upon changes in the power of the input optical signal.