Abstract: A micro-processor includes a clock generator configured to generate a fetch clock, a decoding clock, an execution clock, and a write-back clock that are sequentially enabled; a volatile memory device configured to output pre-stored program data in response to the fetch clock; a command decoder configured to decode the program data in response to the decoding clock and generate a decoding command; an arithmetic device configured to perform an arithmetic operation according to the command of the decoding command in response to the execution clock; and a peripheral circuit device configured to be operated according to the command of the decoding command in response to the write-back clock.

Abstract: An OFDM system includes a frequency-time transformer configured to receive and transform input data to be transmitted to a time-domain sequence; a serial/parallel transformer configured to divide the time-domain sequence into plural sequences; a phase rotating module configured to perform phase rotation in respects to each of the divided time-domain sequences; and a minimum PAPR signal selector configured to select a sequence having a minimum peak-to-average power ratio (PAPR) among the sequences outputted from the phase rotating module.

Abstract: A micro-processor includes a clock generator configured to generate a fetch clock, a decoding clock, an execution clock, and a write-back clock that are sequentially enabled; a volatile memory device configured to output pre-stored program data in response to the fetch clock; a command decoder configured to decode the program data in response to the decoding clock and generate a decoding command; an arithmetic device configured to perform an arithmetic operation according to the command of the decoding command in response to the execution clock; and a peripheral circuit device configured to be operated according to the command of the decoding command in response to the write-back clock.

Abstract: An OFDM system includes a frequency-time transformer configured to receive and transform input data to be transmitted to a time-domain sequence; a serial/parallel transformer configured to divide the time-domain sequence into plural sequences; a phase rotating module configured to perform phase rotation in respects to each of the divided time-domain sequences; and a minimum PAPR signal selector configured to select a sequence having a minimum peak-to-average power ratio (PAPR) among the sequences outputted from the phase rotating module.

Abstract: A power-on reset circuit according to an embodiment of the present invention includes an input control unit configured to generate a default input signal in response to a power-on reset signal and a clock, a counting unit configured to perform a counting operation in response to the default input signal to generate a count offset signal, and a power-on reset unit configured to perform a counting operation in response to the count offset signal to generate the power-on reset signal.

Abstract: A power-on reset circuit according to an embodiment of the present invention includes an input control unit configured to generate a default input signal in response to a power-on reset signal and a clock, a counting unit configured to perform a counting operation in response to the default input signal to generate a count offset signal, and a power-on reset unit configured to perform a counting operation in response to the count offset signal to generate the power-on reset signal.

Abstract: Provided is an STBC transceiving system with LPA-based beamformer, including: an STBC encoder having branches, in number of D, to generate output signals in number of D for an input signal; a beamformer having output antennas in number of D*B, being comprised of beam-forming subarrays in number of D each having the output antennas in number of B to form a downlink beam from the D-numbered output signals of the STBC encoder; and an STBC decoder restoring an original signal by dividing a signal, which is received as one with signals transmitted through a mobile antenna from the D-numbered beam-forming subarrays, into signals in number of D in accordance with the subarrays in consideration of channel characteristics.

Abstract: A Montgomery multiplier for providing security of information used in smart cards from hacking by a differential power analysis attack by minimizing power consumption difference by the input data. More particularly, the Montgomery multiplier applies an asynchronous dual rail lines method wherein two lines DATAFALSE and DATATRUE are used to represent one binary data such that in order to represent binary data ‘0’, a logical high signal is applied to the DATAFALSE line, and a logical low signal is applied to the DATATRUE line. Conversely, to represent binary data ‘1’, a logical low signal is applied to the DATAFALSE line, and a logical high signal is applied to the DATATRUE line. That is, when the data is represented by the asynchronous dual rail lines method, whatever the binary data value is, the same number of logical high states and logical low states are generated. As a result, whatever binary data is to be operated, the power consumption difference of the circuit is minimized.

Abstract: The present invention relates to a data transmission apparatus using an asynchronous dual-rail bus and a method therefor which can reduce power consumption for transferring data by limiting the number of dual-rail buses transferring data when a transmission side transfers an identical data.

Abstract: The present invention disclosed herein is an asynchronous switch for an network on chip application making possible between IP (Intellectual Property) communication among various IPs in the network on chip.

Abstract: Disclosed is an IP module for an SOC which brings easiness in designing system architecture and integration. The IP module of the invention includes a controller for generating a control signal for IP module with reference to a handshake signal and sending a control signal which leads the IP module to process input data in response to handshake signal; and a data processor generating output data and a modified handshake signal after processing a handshake signal and input data under the control of the controller. The present invention makes it possible to design an IP module that is easily reusable and optimized in architecture, lightening effort and time for designing and verifying an SOC by means of the proposed IP module.

Abstract: The present invention relates to a delay-insensitive DI data transfer circuit based on a current-mode multiple-valued logic for transferring data regardless of a delay time of transmission according to a length of wire. The delay-insensitive data transfer circuit of the present invention, in a delay-insensitive data transfer circuit transferring an input request signal and a data signal from a data transmission unit to a data receiving unit, comprises: an encoder for outputting a signal which has been converted to current-level signals in response to voltage-level input of data signal and request signal from the data transmission unit; and a decoder for restoring the voltage-level signals from the current-level signals of the encoder, abstracting a data signal and a request signal from the restored voltage-level signals, and outputting the data signal and the request signal to the data receiving unit.

Abstract: Disclosed is a data transmitting circuit and a method based on a differential value data encoding to reduce a data transmitting time by transmitting an encoded differential value. The circuit comprises an encoder for encoding and outputting a differential value between a currently transmitted data value and a previously transmitted data value, wherein the encoder inverts a phase of one output signal among 2n(namely, N)-output signals in response to n-bit input value and outputs an encoded data value; and a decoder for decoding the output value of the encoder and restoring the original data value, wherein the decoder restores the original data value by adding an output value from the encoder and the previous original data value.

Abstract: An integer transforming device for a moving-picture compression encoder, associated with the H.264 standard, comprising: a first adding/subtracting stage including pluralities of adders/subtracters to execute addition and subtraction for input data, generating data extended by a predetermined bit number; a second adding/subtracting stage including pluralities of adders/subtracters to execute addition and subtraction for a shifted result of output data of the first adding/subtracting stage, generating data extended by a predetermined bit number; a third adding/subtracting stage including pluralities of adders/subtracters to execute addition and subtraction for an operation result of the second adding/subtracting stage, generating data extended by a predetermined bit number; and a fourth adding/subtracting stage including pluralities of adders/subtracters to execute addition and subtraction for a shifted result of the third adding/subtracting stage, generating data extended by a predetermined bit number.

Abstract: Provided is an STBC transceiving system with LPA-based beamformer, including: an STBC encoder having branches, in number of D, to generate output signals in number of D for an input signal; a beamformer having output antennas in number of D*B, being comprised of beam-forming subarrays in number of D each having the output antennas in number of B to form a downlink beam from the D-numbered output signals of the STBC encoder; and an STBC decoder restoring an original signal by dividing a signal, which is received as one with signals transmitted through a mobile antenna from the D-numbered beam-forming subarrays, into signals in number of D in accordance with the subarrays in consideration of channel characteristics.

Abstract: Disclosed is an IP module for an SOC which brings easiness in designing system architecture and integration. The IP module of the invention includes a controller for generating a control signal for IP module with reference to a handshake signal and sending a control signal which leads the IP module to process input data in response to handshake signal; and a data processor generating output data and a modified handshake signal after processing a handshake signal and input data under the control of the controller. The present invention makes it possible to design an IP module that is easily reusable and optimized in architecture, lightening effort and time for designing and verifying an SOC by means of the proposed IP module.

Abstract: The present invention discloses a Montgomery multiplier for an RSA security module secured from a differential power analysis attack.

Abstract: Disclosed is a data transmitting circuit and a method based on a differential value data encoding to reduce a data transmitting time by transmitting an encoded differential value. The circuit comprises an encoder for encoding and outputting a differential value between a currently transmitted data value and a previously transmitted data value, wherein the encoder inverts a phase of one output signal among 2n(namely, N)-output signals in response to n-bit input value and outputs an encoded data value; and a decoder for decoding the output value of the encoder and restoring the original data value, wherein the decoder restores the original data value by adding an output value from the encoder and the previous original data value.

Abstract: The present invention disclosed herein is an asynchronous switch for an network on chip application making possible between IP (Intellectual Property) communication among various IPs in the network on chip.

Abstract: The present invention relates to a delay-insensitive DI data transfer circuit based on a current-mode multiple-valued logic for transferring data regardless of a delay time of transmission according to a length of wire. The delay-insensitive data transfer circuit of the present invention, in a delay-insensitive data transfer circuit transferring an input request signal and a data signal from a data transmission unit to a data receiving unit, comprises: an encoder for outputting a signal which has been converted to current-level signals in response to voltage-level input of data signal and request signal from the data transmission unit; and a decoder for restoring the voltage-level signals from the current-level signals of the encoder, abstracting a data signal and a request signal from the restored voltage-level signals, and outputting the data signal and the request signal to the data receiving unit.