Abstract: A smart design system provides a mobile application design and a simulation function, a business model including the smart design system, and a method of operating the smart design system. A method of operating a smart design system includes selecting at least one product of a plurality of products by searching a database storing information related to the plurality of products. The method includes designing an application that includes the selected at least one product. The designing may be used to produce the application. The method includes providing at least one recommended product of the plurality of products. The recommended product is applicable to the application. The method includes providing a market trend analysis. The market trend analysis is generated by searching for information related to a market trend of at least one of the plurality of products applicable to the application.

Abstract: A method and apparatus to reproduce a media file including reading mapping information from a predetermined position of the media file, searching for a sound field effect file of the media file by referring to the mapping information, and setting an equalizer of the audio data on the basis of the sound field effect file. A user can reproduce a media file by using an optimized equalizer of each media file even though the user himself does not set the equalizer. Also, since an equalizer setting of the reproducing apparatus can be applied to another reproducing apparatus, a user can enjoy listening to a media file in the other reproducing apparatus under the same reproducing conditions as those of the reproducing apparatus.

Abstract: A method and apparatus to reproduce a media file including reading mapping information from a predetermined position of the media file, searching for a sound field effect file of the media file by referring to the mapping information, and setting an equalizer of the audio data on the basis of the sound field effect file. A user can reproduce a media file by using an optimized equalizer of each media file even though the user himself does not set the equalizer. Also, since an equalizer setting of the reproducing apparatus can be applied to another reproducing apparatus, a user can enjoy listening to a media file in the other reproducing apparatus under the same reproducing conditions as those of the reproducing apparatus.

Abstract: A self-refresh method and refresh control circuit of a semiconductor memory device, wherein after the self-refresh mode starts, the burst refresh mode is performed prior to the self-refresh mode; or the self-refresh mode is performed immediately after going into the self-refresh mode, and the burst refresh mode is performed at the completion of the self-refresh mode, and then the burst refresh mode is converted to the normal access mode; or the burst refresh mode is performed before and after the self-refresh mode, thereby shortening a refresh regulation time and securing a stable refresh of the memory cells.

Abstract: A high density semiconductor device is provided with an improved voltage pumping (bootstrapping) circuit. The voltage pumping circuit generates at an initial power-up state a first output voltage which is substantially identical to the memory device source supply voltage. The pumping circuit then pumps the first output voltage up to a second output voltage which is higher than the first output voltage. The pumping operation is achieved prior to or upon the semiconductor memory device being enabled in response to a series of pulses output from an oscillator.

Abstract: A semiconductor memory device divided into a number of main blocks each main block having a number of subblocks selects a single main block and enables the subblocks of the selected main block, so as to reduce the power consumptions. The semiconductor memory device includes a block selector for selecting one of the main blocks in response to row address signals, a number of first boost circuits for selecting the subblocks of the selected main block in response to the row address signals, and a number of second boost circuits adapted to be disabled in response to the row address signals.

Abstract: A sense amplifier and high performance DRAM, in combination, has in the DRAM at least one row of memory cells, whereby the memory cells of the row may be arranged in respective columns with memory cells of other rows. Each of the memory cells has a transistor and a capacitor connected serially between one of bit lines successively along the row and a fixed voltage source. Word lines are respectively connected to gates of the transistors of the memory cells for activating the memory cell selectively according to row address. The sense amplifier has a cross-coupled bistable flip-flop connecting the bit lines to each other in the row. A latch transistor connected to the flip-flop detects and amplifies a voltage difference between the bit lines. The bit lines are equalized and precharged with a reference voltage in response to a clock control signal. A cross-coupled pair of transistors also connecting the bit lines to each other transfer a charging voltage to the bit lines.