Abstract: Provided is a binder for a secondary battery including a copolymer including repeating units of the Chemical Formula 1, Chemical Formula 2, Chemical Formula 3, and Chemical Formula 4 disclosed herein. When the binder for a secondary battery is applied to a negative electrode and a secondary battery, expansion of the negative electrode may be effectively suppressed. Furthermore, the binder for a secondary battery has improved adhesion to effectively suppress exfoliation and desorption of a negative electrode, thereby manufacturing a secondary battery having significantly improved charge/discharge cycle characteristics and battery performance by using the binder.

Abstract: An apparatus of tilting a seat cushion of a vehicle, includes a tilting motor, a pinion gear, a sector gear, and a tilting link which perform the tilting operation of the seat cushion and exert a binding force in a tilted state of the seat cushion and are provided to be connected to both of one side and the other side of a seat cushion frame, and has two sector gears positioned on left and right sides and connected to each other by a connection bar so that, by strengthening a binding force of the front portion of the seat cushion, it is possible to secure the safety of passengers in the event of a collision.

Abstract: There is provided a power semiconductor device including: a first semiconductor region of a first conductivity type; second semiconductor regions formed in the first semiconductor region and being of a second conductivity type; a well region formed above the second semiconductor regions and being of the second conductivity type; and a source region formed in the well region and being of the first conductivity type, wherein the second semiconductor regions include 1 to n layers formed from a lower portion of the device extending a in a direction of height of the device, and in the case that the widest width of the of the second semiconductor region of the nth layer is Pn, P1<Pn (n?2).

Abstract: A power semiconductor device may include a first conductivity type semiconductor substrate, a super-junction portion disposed on the first conductivity type semiconductor substrate and including a first conductivity type pillar and a second conductivity type pillar arranged in an alternating manner, and a three-dimensional (3D) gate portion disposed on the first conductivity type pillar. The 3D gate portion is disposed on the first conductivity type pillar to reduce the widths of the first and second conductivity type pillars, thereby effectively reducing a device size.

Abstract: There is provided a power semiconductor device, including a first conductive type drift layer; a second conductive type body layer formed on the drift layer, a second conductive type collector layer formed below the drift layer; a first gate formed by penetrating through the body layer and a portion of the drift layer, a first conductive type emitter layer formed in the body layer and formed to be spaced apart from the first gate, a second gate covering upper portions of the body layer and the emitter layer and formed as a flat type gate on the first gate, and a segregation stop layer formed between contact surfaces of the first and second gates with the body layer, the emitter layer, and the drift layer.

Abstract: There is provided an insulated gate bipolar transistor including: a first semiconductor area of a first conductivity type; a second semiconductor area of a second conductivity type formed on one surface of the first semiconductor area; third semiconductor areas of the first conductivity type continuously formed in a length direction on one surface of the second semiconductor area; a plurality of trenches formed between the third semiconductor areas, extending to an inside of the second semiconductor area, and being continuous in the length direction; a fourth semiconductor area of the second conductivity type formed on one surface of the third semiconductor areas, insulation layers formed inside the trenches; gate electrodes buried inside the insulation layers; and a barrier layer formed in at least one of locations corresponding to the third semiconductor areas inside the second semiconductor area.

Abstract: Disclosed herein is a semiconductor device including: a source electrode formed on one side of an N-type AlGaN layer; N-type and P-type AlGaN layers formed on the other side of the P-type AlGaN layer and formed in a direction perpendicular to the source electrode; a gate electrode formed on one side of the N-type and P-type AlGaN layers; and a drain electrode formed on the other side of the N-type and P-type AlGaN layers.

Abstract: A power semiconductor device may include a first conductivity type first semiconductor region; a second conductivity type second semiconductor region formed on an upper portion of the first semiconductor region; a first conductivity type third semiconductor region formed in an upper inner side of the second semiconductor region; a trench gate formed to penetrate through a portion of the first semiconductor region from the third semiconductor region; and a first conductivity type fourth semiconductor region formed below the second semiconductor region while being spaced apart from the trench gate.

Abstract: A power semiconductor device may include: an active region in which a current flows through a channel formed when the device being turned on; a termination region disposed around the active region; a first semiconductor region of a first conductive type disposed in the termination region in a direction from the active region to the termination region; and a second semiconductor region of a second conductive type disposed in the termination region in the direction from the active region to the termination region, the first semiconductor region and the second semiconductor region being disposed alternately.

Abstract: A power semiconductor device may include: a base substrate including a first conductive type drift layer; a second conductive type semiconductor substrate disposed on the other surface of the base substrate; a first conductive type diffusion layer disposed in the base substrate and having an impurity concentration higher than that of the drift layer; a second conductive type well layer disposed inside of one surface of the base substrate; a trench formed from one surface of the base substrate including the well layer so as to penetrate through the diffusion layer in a depth direction; a first insulation film disposed on a surface of the base substrate; and a first electrode disposed in the trench. A peak point of an impurity doping concentration of the diffusion layer in a transverse direction may be positioned in a region contacting a side surface of the trench.

Abstract: A power semiconductor device may include a first conductivity type semiconductor substrate, a super-junction portion disposed on the first conductivity type semiconductor substrate and including a first conductivity type pillar and a second conductivity type pillar arranged in an alternating manner, and a three-dimensional (3D) gate portion disposed on the first conductivity type pillar. The 3D gate portion is disposed on the first conductivity type pillar to reduce the widths of the first and second conductivity type pillars, thereby effectively reducing a device size.

Abstract: A power semiconductor device may include: an n-drift part; a gate disposed in an upper portion of the n-drift part; an active part disposed to be in contact with the gate; an emitter part disposed in the active part and disposed to be in contact with the gate; an inactive part disposed to be spaced apart from the active part; a floating part disposed in the inactive part; and a dummy gate disposed to surround the inactive part in order to prevent a hole pass between the active part and the inactive part.

Abstract: A power semiconductor device may include: a first conductivity-type first semiconductor region; a second conductivity-type second semiconductor region disposed above the first semiconductor region; a trench gate penetrating through the second semiconductor region and a portion of the first semiconductor region; a third semiconductor region disposed on both sides of the trench gate and disposed on an inner side of an upper portion of the second semiconductor region; and a device protective region disposed in the third semiconductor region.

Abstract: Disclosed herein is a power semiconductor device including: a base substrate having one surface and the other surface and formed of a first conductive type drift layer; a first conductive type diffusion layer formed on one surface of the base substrate and having a concentration higher than that of the first conductive type drift layer; and a trench formed so as to penetrate through the second conductive type well layer and the first conductive type diffusion layer from one surface of the base substrate including the second conductive type well layer in a thickness direction.

Abstract: Disclosed herein is a power semiconductor device. The power semiconductor device includes a second conductive type first junction termination extension (JTE) layer that is formed so as to be in contact with one side of the second conductive type well layer, a second conductive type second JTE layer that is formed on the same line as the second conductive type first JTE layer, and is formed so as to be spaced apart from the second conductive type first JTE layer in a length direction of the substrate, and a poly silicon layer that is formed so as to be in contact with the second conductive type well layer and an upper portion of the second conductive type first JTE layer.

Abstract: A semiconductor device may include a drift layer having a first conductivity-type; a body region having a second conductivity-type and disposed on the drift layer; first semiconductor regions having the second conductivity-type and disposed to be spaced apart from each other below the drift layer; and second semiconductor regions having the first conductivity-type and disposed between the first semiconductor regions below the drift layer.

Abstract: There is provided a power semiconductor device including a contact formed in an active region, a trench gate extendedly formed from the first region into a first termination region and formed alternately with the contact, a first conductive well formed between the contact of the active region and the trench gate, a first conductive well extending portion formed in the first termination region and a part of a second termination region, and a first conductive field limiting ring formed in the second termination region and contacting the well extending portion.

Abstract: There is provided a power semiconductor device, including: a first conductive type drift layer, a second conductive type termination layer formed on an upper portion of an edge of the drift layer, and a high concentration first conductive type channel stop layer formed on a side surface of the edge of the drift layer.

Abstract: Disclosed herein is a power semiconductor device including: a base substrate having one surface and the other surface and formed of a first conductive type drift layer; a first conductive type diffusion layer formed on one surface of the base substrate and having a concentration higher than that of the first conductive type drift layer; and a trench formed so as to penetrate through the second conductive type well layer and the first conductive type diffusion layer from one surface of the base substrate including the second conductive type well layer in a thickness direction.

Abstract: A power semiconductor device may include: an active region in which a current flows through a channel formed when the device being turned on; a termination region disposed around the active region; a first semiconductor region of a first conductive type disposed in the termination region in a direction from the active region to the termination region; and a second semiconductor region of a second conductive type disposed in the termination region in the direction from the active region to the termination region, the first semiconductor region and the second semiconductor region being disposed alternately.