Patents by Inventor Dong-Soo Woo
Dong-Soo Woo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11469306Abstract: A semiconductor device including a substrate having isolation films and active regions that are defined by the isolation films. The active regions extend in a first direction. A first trench is disposed on the substrate. Second trenches are disposed in the active regions. A filling film is disposed in the first trench. First gate patterns are disposed on the filling film in the first trench. Second gate patterns are disposed in the second trenches. The second gate patterns extend in a second direction that is different from the first direction. The filling film includes at least one material selected from a semiconductor material film and a metal.Type: GrantFiled: August 17, 2020Date of Patent: October 11, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jee-Sun Lee, Dong Soo Woo, Nam Ho Jeon
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Publication number: 20210126098Abstract: A semiconductor device including a substrate having isolation films and active regions that are defined by the isolation films. The active regions extend in a first direction. A first trench is disposed on the substrate. Second trenches are disposed in the active regions. A filling film is disposed in the first trench. First gate patterns are disposed on the filling film in the first trench. Second gate patterns are disposed in the second trenches. The second gate patterns extend in a second direction that is different from the first direction. The filling film includes at least one material selected from a semiconductor material film and a metal.Type: ApplicationFiled: August 17, 2020Publication date: April 29, 2021Inventors: Jee-Sun LEE, Dong Soo WOO, Nam Ho JEON
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Patent number: 9685519Abstract: A semiconductor device includes a field regions in a substrate to define active regions, gate trenches including active trenches disposed across the active region and field trenches in the field regions, and word lines that fill the gate trenches and extend in a first direction. The word lines include active gate electrodes occupying the active trenches, and field gate electrodes occupying the field trenches. The bottom surface of each field gate electrode, which is disposed between active regions that are adjacent to each other and have one word line therebetween, is disposed at a higher level than the bottom surfaces of the active gate electrodes.Type: GrantFiled: June 2, 2015Date of Patent: June 20, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Na-Ra Kim, Seung-Hwan Kim, Sung-Hee Lee, Dae-Sin Kim, Ji-Young Kim, Dong-Soo Woo
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Patent number: 9536884Abstract: A semiconductor device can include a substrate including a plurality of active regions having a long axis in a first direction and a short axis in a second direction, the plurality of active regions being repeatedly and separately positioned along the first and second directions, an isolation film defining the plurality of active regions, a plurality of word lines extending across the plurality of active regions and the isolation film, and a positive fixed charge containing layer covering at least a portion of the plurality of word lines, respectively.Type: GrantFiled: August 4, 2014Date of Patent: January 3, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Soo Kim, Dong-Soo Woo, Se-myeong Jang
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Patent number: 9293180Abstract: A memory device comprises: a memory cell array comprising first and second word lines located adjacent to each other, a first memory cell connected to the first word line, and a second memory cell connected to the second word line and located adjacent to the first memory cell; and a word line voltage supplying unit that transitions a word line voltage of the first word line from a first word line voltage to a second word line voltage, in response to a first control signal. A transition control unit generates the first control signal for controlling a pulse of the word line voltage of the first word line in a transition period from the first word line voltage to the second word line voltage in such a way that a transition waveform profile from the first word line voltage to the second word line voltage is different from a transition waveform profile from the second word line voltage to the first word line voltage.Type: GrantFiled: May 29, 2014Date of Patent: March 22, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eui-chul Jeong, Sung-hee Lee, Dae-sin Kim, Seung-hwan Kim, Dae-sun Kim, Sua Kim, Dong-soo Woo, Na-ra Kim
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Publication number: 20150263113Abstract: A semiconductor device includes a field regions in a substrate to define active regions, gate trenches including active trenches disposed across the active region and field trenches in the field regions, and word lines that fill the gate trenches and extend in a first direction. The word lines include active gate electrodes occupying the active trenches, and field gate electrodes occupying the field trenches. The bottom surface of each field gate electrode, which is disposed between active regions that are adjacent to each other and have one word line therebetween, is disposed at a higher level than the bottom surfaces of the active gate electrodes.Type: ApplicationFiled: June 2, 2015Publication date: September 17, 2015Inventors: NA-RA KIM, SEUNG-HWAN KIM, SUNG-HEE LEE, DAE-SIN KIM, JI-YOUNG KIM, DONG-SOO WOO
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Patent number: 9082850Abstract: A semiconductor device includes a field regions in a substrate to define active regions, gate trenches including active trenches disposed across the active region and field trenches in the field regions, and word lines that fill the gate trenches and extend in a first direction. The word lines include active gate electrodes occupying the active trenches, and field gate electrodes occupying the field trenches. The bottom surface of each field gate electrode, which is disposed between active regions that are adjacent to each other and have one word line therebetween, is disposed at a higher level than the bottom surfaces of the active gate electrodes.Type: GrantFiled: August 6, 2013Date of Patent: July 14, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Na-Ra Kim, Seung-Hwan Kim, Sung-Hee Lee, Dae-Sin Kim, Ji-Young Kim, Dong-Soo Woo
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Publication number: 20150194438Abstract: A semiconductor device can include a substrate including a plurality of active regions having a long axis in a first direction and a short axis in a second direction, the plurality of active regions being repeatedly and separately positioned along the first and second directions, an isolation film defining the plurality of active regions, a plurality of word lines extending across the plurality of active regions and the isolation film, and a positive fixed charge containing layer covering at least a portion of the plurality of word lines, respectively.Type: ApplicationFiled: August 4, 2014Publication date: July 9, 2015Inventors: Jun-Soo Kim, Dong-Soo Woo, Se-myeong Jang
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Publication number: 20140362637Abstract: A memory device comprises: a memory cell array comprising first and second word lines located adjacent to each other, a first memory cell connected to the first word line, and a second memory cell connected to the second word line and located adjacent to the first memory cell; and a word line voltage supplying unit that transitions a word line voltage of the first word line from a first word line voltage to a second word line voltage, in response to a first control signal. A transition control unit generates the first control signal for controlling a pulse of the word line voltage of the first word line in a transition period from the first word line voltage to the second word line voltage in such a way that a transition waveform profile from the first word line voltage to the second word line voltage is different from a transition waveform profile from the second word line voltage to the first word line voltage.Type: ApplicationFiled: May 29, 2014Publication date: December 11, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Eui-chul Jeong, Sung-hee Lee, Dae-sin Kim, Seung-hwan Kim, Dae-sun Kim, Sua Kim, Dong-soo Woo, Na-ra Kim
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Patent number: 8884340Abstract: A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.Type: GrantFiled: November 17, 2011Date of Patent: November 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Young Kim, Gyo-Young Jin, Hyeong-Sun Hong, Yong-Chul Oh, Yoo-Sang Hwang, Sung-Kwan Choi, Dong-Soo Woo, Hyun-Woo Chung
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Patent number: 8835252Abstract: Methods of fabricating semiconductor device are provided including forming first through third silicon crystalline layers on first through third surfaces of an active region; removing the first silicon crystalline layer to expose the first surface; forming a bit line stack on the exposed first surface; forming bit line sidewall spacers on both side surfaces of the bit line stack to be vertically aligned with portions of the second and third silicon crystalline layers of the active region; removing the second and third silicon crystalline layers disposed under the bit line sidewall spacers to expose the second and third surfaces of the active region; and forming storage contact plugs in contact with the second and third surfaces of the active region.Type: GrantFiled: May 24, 2013Date of Patent: September 16, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-Seok Moon, Jae-Rok Kahng, Hyun-Seung Song, Dong-Soo Woo, Sang-Hyun Lee, Hyun-Jung Lee
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Publication number: 20140110786Abstract: A semiconductor device includes a field regions in a substrate to define active regions, gate trenches including active trenches disposed across the active region and field trenches in the field regions, and word lines that fill the gate trenches and extend in a first direction. The word lines include active gate electrodes occupying the active trenches, and field gate electrodes occupying the field trenches. The bottom surface of each field gate electrode, which is disposed between active regions that are adjacent to each other and have one word line therebetween, is disposed at a higher level than the bottom surfaces of the active gate electrodes.Type: ApplicationFiled: August 6, 2013Publication date: April 24, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: NA-RA KIM, SEUNG-HWAN KIM, SUNG-HEE LEE, DAE-SIN KIM, JI-YOUNG KIM, DONG-SOO WOO
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Publication number: 20130344666Abstract: Methods of fabricating semiconductor device are provided including forming first through third silicon crystalline layers on first through third surfaces of an active region; removing the first silicon crystalline layer to expose the first surface; forming a bit line stack on the exposed first surface; forming bit line sidewall spacers on both side surfaces of the bit line stack to be vertically aligned with portions of the second and third silicon crystalline layers of the active region; removing the second and third silicon crystalline layers disposed under the bit line sidewall spacers to expose the second and third surfaces of the active region; and forming storage contact plugs in contact with the second and third surfaces of the active region.Type: ApplicationFiled: May 24, 2013Publication date: December 26, 2013Inventors: Joon-Seok Moon, Jae-Rok Kahng, Hyun-Seung Song, Dong-Soo Woo, Sang-Hyun Lee, Hyun-Jung Lee
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Patent number: 8610191Abstract: Semiconductor devices and dynamic random access memory devices including a buried gate electrode are provided, the semiconductor devices include a substrate with a gate trench, a buried gate electrode partially filling the inside of the gate trench, a capping layer pattern in the gate trench and over the buried gate electrode, source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode, and a gate insulation layer interposed between the trench and the buried gate electrode. The capping layer pattern includes a high-k material layer that directly contacts an upper surface of the buried gate electrode.Type: GrantFiled: December 2, 2010Date of Patent: December 17, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Joon-Seok Moon, Dong-Soo Woo, Jaerok Kahng, Jinwoo Lee, Keeshik Park
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Publication number: 20130043519Abstract: A device includes a semiconductor substrate and a gate insulation film lining a trench in an active region of the substrate. A gate electrode pattern is recessed in the trench on the gate insulation film and has an upper surface that has a nonuniform height. A dielectric pattern may be disposed on the gate electrode pattern in the trench.Type: ApplicationFiled: August 20, 2012Publication date: February 21, 2013Inventors: Joon-seok Moon, Jae-rok Kahng, Jin-woo Lee, Sung-sam Lee, Dong-soo Woo, Kyoung-ho Jung, Jung-kyu Jung
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Publication number: 20120299090Abstract: A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.Type: ApplicationFiled: November 17, 2011Publication date: November 29, 2012Inventors: Ji-Young Kim, Gyo-Young Jin, Hyeong-Sun Hong, Yong-Chul Oh, Yoo-Sang Hwang, Sung-Kwan Choi, Dong-Soo Woo, Hyun-Woo Chung
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Patent number: 8184471Abstract: A DRAM device having a plurality of memory blocks, including edge-located memory blocks and adjacent central memory blocks. An edge-located memory block shares a sense amplifier with an adjacent central memory block. The memory cells in the edge-located memory block include data storage capacitors having a greater capacitance value than data storage capacitors in the memory cells in the adjacent central memory block. The data storage capacitors in edge-located memory cells may have greater surface area than data storage capacitors in the central memory cells. The data storage capacitors in edge-located memory cells may be formed by connecting in parallel two data storage capacitors of the shape and size of data storage capacitors used in each of the memory cells of the adjacent central memory block.Type: GrantFiled: April 1, 2009Date of Patent: May 22, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Soo Woo, Jong-Soo Kim
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Publication number: 20110169066Abstract: Semiconductor devices and dynamic random access memory devices including a buried gate electrode are provided, the semiconductor devices include a substrate with a gate trench, a buried gate electrode partially filling the inside of the gate trench, a capping layer pattern in the gate trench and over the buried gate electrode, source/drain regions below an upper surface of the substrate and adjacent to both sides of the buried gate electrode, and a gate insulation layer interposed between the trench and the buried gate electrode. The capping layer pattern includes a high-k material layer that directly contacts an upper surface of the buried gate electrode.Type: ApplicationFiled: December 2, 2010Publication date: July 14, 2011Inventors: Joon-Seok MOON, Dong-Soo WOO, Jaerok KAHNG, Jinwoo LEE, Keeshik PARK
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Patent number: 7799643Abstract: Methods of fabricating a semiconductor device having a self-aligned contact plug are provided. Methods include forming a lower insulating layer on a semiconductor substrate, forming a plurality of interconnection patterns parallel to each other on the lower insulating layer; forming an upper insulating layer that is configured to fill between the interconnection patterns, and forming a plurality of first mask patterns crossing the plurality of interconnection patterns, ones of the plurality of first mask patterns parallel to each other on the semiconductor substrate having the upper insulating layer.Type: GrantFiled: April 30, 2008Date of Patent: September 21, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Nam-Jung Kang, Dong-Soo Woo, Hyeong-Sun Hong, Dong-Hyun Kim
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Publication number: 20100081395Abstract: A DRAM device having a plurality of memory blocks, including edge-located memory blocks and adjacent central memory blocks. An edge-located memory block shares a sense amplifier with an adjacent central memory block. The memory cells in the edge-located memory block include data storage capacitors having a greater capacitance value than data storage capacitors in the memory cells in the adjacent central memory block. The data storage capacitors in edge-located memory cells may have greater surface area than data storage capacitors in the central memory cells. The data storage capacitors in edge-located memory cells may be formed by connecting in parallel two data storage capacitors of the shape and size of data storage capacitors used in each of the memory cells of the adjacent central memory block.Type: ApplicationFiled: April 1, 2009Publication date: April 1, 2010Inventors: Dong-Soo Woo, Jong-Soo Kim