Abstract: A self-test circuit and method for efficiently testing a semiconductor memory device are described. A plurality of memory cells is provided with each memory cell comprising a storage location with a data value stored therein. A control circuit is provided for controlling a test of the memory cells. A shift multiplexer is provided for generating a write signal responsive to a shift signal received over a connection to the control circuit. A latch multiplexer is provided for generating a read signal responsive to a latch signal received over a connection to the control circuit. A plurality of output registers are provided with each output register connected to the latch multiplexer and including a connection for reading the data value from the storage location of one of the memory cells responsive to the latch multiplexer and a further connection for generating the data value as an output.