Abstract: An aerosol generating device includes: a housing including a hole for receiving an aerosol generating article and a guide apart from the hole; and a cover configured to move along the guide between a first position and a second position to open or close the hole, wherein the hole is open when the cover is located in the first position, and the hole is closed when the cover is located in the second position.

Abstract: The present disclosure provides autotaxin (ATX) inhibitor compounds and compositions including said compounds. The present disclosure also provides methods of using said compounds and compositions for inhibiting ATX. Also provided are methods of preparing said compounds and compositions, and synthetic precursors of said compounds.

Abstract: One or more embodiments relate to an aerosol generating article including: a first portion including an aerosol generating element; a second portion including a cooling element; a third portion including a tobacco element; and a fourth portion including a filter element, wherein the first through fourth portions are sequentially arranged in a longitudinal direction of the aerosol generating article.

Abstract: A method for unlocking the electronic device includes displaying a screen for verifying a registered user, determining whether a user is a registered user in the electronic device based on a user input to the screen for verifying a registered user, and unlocking the electronic device when the user is determined to be the registered user.

Abstract: Provided is an aerosol generating apparatus including: a susceptor configured to heat an aerosol generating article inserted into an accommodation space of the aerosol generating apparatus; an induction coil arranged around the susceptor and configured to heat the susceptor by induction heating; a switching module configured to switch an electrical path of the induction coil; and a controller electrically connected to the switching module and configured to detect insertion of the aerosol generating article on the basis of a change in an inductance of the induction coil by setting a control mode for the induction coil to a reception mode, and when the insertion of the aerosol generating article is detected, switch the control mode to a transmission mode for activating the induction heating, via the switching module.

Abstract: Provided are an electric appliance and a method of manufacturing the same, the electric appliance having a smaller size and a reduced overall weight by preventing a fluid from flowing into a space unrelated to a heating component in a state where the fluid fills its case. The electric appliance includes: a case including a first space and a second space communicated to each other; a first component disposed in the first space; a second component disposed in the second space; a connection portion electrically connecting the first component and the second component to each other; and a potting pattern including a resin material and formed in the first space.

Abstract: An aerosol generating device includes: a housing including a hole for receiving an aerosol generating article and a guide apart from the hole; and a cover configured to move along the guide between a first position and a second position to open or close the hole, wherein the hole is open when the cover is located in the first position, and the hole is closed when the cover is located in the second position.

Abstract: An optical imaging system includes a first lens having positive refractive power, a convex object-side surface and a concave image-side surface; a second lens having negative refractive power, a convex object-side surface and a concave image-side surface; a third lens having positive refractive power; a fourth lens having negative refractive power; a fifth lens; a sixth lens having a convex object-side surface; and a seventh lens having negative refractive power, a convex object-side surface and a concave image-side surface, wherein the first to seventh lenses are disposed in order from an object side toward an imaging plane, wherein the optical imaging system has a total of seven lenses, and wherein 0<f1/f<1.5, ?5<f2/f<?1, ?10<f3/f/100<2, ?5<f4/f/100<1, ?0.5<f1/f2<0, ?1<f1/f3<3, 70°<FOV×(IMG HT/f), and |f1/f4/n4|<0.3 are satisfied.

Abstract: An optical imaging system includes a first lens having positive refractive power, a second lens having negative refractive power, a third lens, a fourth lens, a fifth lens, a sixth lens, a seventh lens, and an eighth lens disposed in order from an object side. A refractive index of the second lens is greater than a refractive index of each of the first lens and the third lens. The optical imaging system satisfies TTL/(2×IMG HT)<0.6 and 0<f1/f<1.4, where TTL is a distance on an optical axis from an object-side surface of the first lens to an imaging plane, IMG HT is half a diagonal length of the imaging plane, f is a total focal length of the optical imaging system, and f1 is a focal length of the first lens.

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

Abstract: A nonvolatile memory device includes a data path; and a FIFO memory including a plurality of registers connected to the data path. The plurality of registers sequentially receive data from the data path in response to data path input clocks and sequentially output the received data to an input/output pad in response to data path output clocks. The data path output clocks are clocks that are generated by delaying the data path input clocks as long as a delay time.

Abstract: A nonvolatile memory device includes a data path; and a FIFO memory including a plurality of registers connected to the data path. The plurality of registers sequentially receive data from the data path in response to data path input clocks and sequentially output the received data to an input/output pad in response to data path output clocks. The data path output clocks are clocks that are generated by delaying the data path input clocks as long as a delay time.

Abstract: A nonvolatile memory device includes a data path; and a FIFO memory including a plurality of registers connected to the data path. The plurality of registers sequentially receive data from the data path in response to data path input clocks and sequentially output the received data to an input/output pad in response to data path output clocks. The data path output clocks are clocks that are generated by delaying the data path input clocks as long as a delay time.

Abstract: A nonvolatile memory device includes a data path; and a FIFO memory including a plurality of registers connected to the data path. The plurality of registers sequentially receive data from the data path in response to data path input clocks and sequentially output the received data to an input/output pad in response to data path output clocks. The data path output clocks are clocks that are generated by delaying the data path input clocks as long as a delay time.

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of cell strings each having a plurality of memory cells stacked in a direction perpendicular to a substrate, and a peripheral circuit region including a plurality of transistors electrically connected to the memory cell array through a plurality of conductive lines. Each of the transistors includes a gate electrode crossing an active region of the substrate in a first direction and source and drain regions in the active region at the opposite sides of the gate electrode. In at least one of the transistors, the number of source contact plugs connected to the source region is different from the number of drain contact plugs connected to the drain region.