Abstract: A method may include, but is not limited to, receiving a measurement including a metrology parameter for a layer of a metrology target and an alignment mark from an overlay metrology tool prior to a lithography process; deriving a merit figure from the metrology parameter and the alignment mark; deriving a correction factor from the merit figure; providing the correction factor to the lithography process via a feed forward process; receiving an additional measurement including an additional metrology parameter for the layer and an additional layer from an additional overlay metrology tool after the lithography process; deriving an adjustment from the additional metrology parameter; and providing the adjustment to the lithography process via a feedback process.

Abstract: Various methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers are provided. One method for creating a dynamic sampling scheme for a process during which measurements are performed on wafers includes performing the measurements on all of the wafers in at least one lot at all measurement spots on the wafers. The method also includes determining an optimal sampling scheme, an enhanced sampling scheme, a reduced sampling scheme, and thresholds for the dynamic sampling scheme for the process based on results of the measurements. The thresholds correspond to values of the measurements at which the optimal sampling scheme, the enhanced sampling scheme, and the reduced sampling scheme are to be used for the process.

Abstract: A process control system may include a controller configured to receive after-development inspection (ADI) data after a lithography step for the current layer from an ADI tool, receive after etch inspection (AEI) overlay data after an exposure step of the current layer from an AEI tool, train a non-zero offset predictor with ADI data and AEI overlay data to predict a non-zero offset from input ADI data, generate values of the control parameters of the lithography tool using ADI data and non-zero offsets generated by the non-zero offset predictor, and provide the values of the control parameters to the lithography tool for fabricating the current layer on the at least one production sample.

Abstract: Target designs methods and targets are provided, in which at least some of the differentiation between target elements and their background is carried out by segmenting either of them. Directed self-assembly (DSA) processes are used to generate fine segmentation, and various characteristics of the polymer lines and their guiding lines are used to differentiate target elements from their background. Target designs and design principles are disclosed in relation to the DSA process, as well as optimization of the DSA process to yield high metrology measurement accuracy in face of production inaccuracies. Furthermore, designs and methods are provided for enhancing and using ordered regions of a DSA-produced polymer surface as target elements and as hard masks for production processes. The targets and methods may be configured to enable metrology measurements using polarized light to distinguish target elements or DSA features.

Abstract: The invention may be embodied in a system and method for monitoring and controlling feedback control in a manufacturing process, such as an integrated circuit fabrication process. The process control parameters may include translation, rotation, magnification, dose and focus applied by a photolithographic scanner or stepper operating on silicon wafers. Overlay errors are used to compute measured parameters used in the feedback control process. Statistical parameters are computed, normalized and graphed on a common set of axes for at-a-glance comparison of measured parameters and process control parameters to facilitate the detection of problematic parameters. Parameter trends and context relaxation scenarios are also compared graphically. Feedback control parameters, such as EWMA lambdas, may be determined and used as feedback parameters for refining the APC model that computes adjustments to the process control parameters based on the measured parameters.

Abstract: A method may include, but is not limited to, receiving a measurement including a metrology parameter for a layer of a metrology target and an alignment mark from an overlay metrology tool prior to a lithography process; deriving a merit figure from the metrology parameter and the alignment mark; deriving a correction factor from the merit figure; providing the correction factor to the lithography process via a feed forward process; receiving an additional measurement including an additional metrology parameter for the layer and an additional layer from an additional overlay metrology tool after the lithography process; deriving an adjustment from the additional metrology parameter; and providing the adjustment to the lithography process via a feedback process.

Abstract: Methods and corresponding metrology modules and systems, which measure metrology parameter(s) of a previous layer of a metrology target and/or an alignment mark, prior to producing a current layer of the metrology target, derive merit figure(s) from the measured metrology parameter(s) to indicate an inaccuracy, and compensate for the inaccuracy to enhance subsequent overlay measurements of the metrology target. In an example embodiment, methods and corresponding metrology modules and systems use stand-alone metrology tool(s) and track-integrated metrology tool(s) at distinct measurement patterns to address separately different aspects of variation among wafers.

Abstract: A process control system may include a controller configured to receive after-development inspection (ADI) data after a lithography step for the current layer from an ADI tool, receive after etch inspection (AEI) overlay data after an exposure step of the current layer from an AEI tool, train a non-zero offset predictor with ADI data and AEI overlay data to predict a non-zero offset from input ADI data, generate values of the control parameters of the lithography tool using ADI data and non-zero offsets generated by the non-zero offset predictor, and provide the values of the control parameters to the lithography tool for fabricating the current layer on the at least one production sample.

Abstract: Various methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers are provided. One method for creating a dynamic sampling scheme for a process during which measurements are performed on wafers includes performing the measurements on all of the wafers in at least one lot at all measurement spots on the wafers. The method also includes determining an optimal sampling scheme, an enhanced sampling scheme, a reduced sampling scheme, and thresholds for the dynamic sampling scheme for the process based on results of the measurements. The thresholds correspond to values of the measurements at which the optimal sampling scheme, the enhanced sampling scheme, and the reduced sampling scheme are to be used for the process.

Abstract: An overlay target for use in imaging based metrology is disclosed. The overlay target includes a plurality of target structures including three or more target structures, each target structure including a set of two or more pattern elements, wherein the target structures are configured to provide metrology information pertaining to different pitches, different coverage ratios, and linearity. Pattern elements may be separated from adjacent pattern elements by non-uniform distance; pattern elements may have non-uniform width; or pattern elements may be designed to demonstrate a specific offset as compared to pattern elements in a different layer.

Abstract: Various methods and systems for creating or performing a dynamic sampling scheme for a process during which measurements are performed on wafers are provided. One method for creating a dynamic sampling scheme for a process during which measurements are performed on wafers includes performing the measurements on all of the wafers in at least one tot at all measurement spots on the wafers. The method also includes determining an optimal sampling scheme, an enhanced sampling scheme, a reduced sampling scheme, and thresholds for the dynamic sampling scheme for the process based on results of the measurements. The thresholds correspond to values of the measurements at which the optimal sampling scheme, the enhanced sampling scheme, and the reduced sampling scheme are to be used for the process.

Abstract: Metrology targets, design files, and design and production methods thereof are provided. The metrology targets are hybrid in that they comprise at least one imaging target structure configured to be measurable by imaging and at least one scatterometry target structure configured to be measurable by scatterometry. Thus, the hybrid targets may be measured by imaging and scatterometry simultaneously or alternatingly and/or the measurement techniques may be optimized with respect to wafer regions and other spatial parameters, as well as with respect to temporal process parameters. The hybrid targets may be used to monitor process parameters, for example via comparative overlay measurements and/or high resolution measurements.

Abstract: A method for monitoring mask focus includes measuring profile asymmetries in a target feature including sub-resolution assist features and deriving a focus response based on a known correlation between the profile and focus of a corresponding mask. A computer system in a lithographic process may adjust mask focus based on such derived information to conform to a desired fabrication process.

Abstract: Methods and corresponding metrology modules and systems, which measure metrology parameter(s) of a previous layer of a metrology target and/or an alignment mark, prior to producing a current layer of the metrology target, derive merit figure(s) from the measured metrology parameter(s) to indicate an inaccuracy, and compensate for the inaccuracy to enhance subsequent overlay measurements of the metrology target. In an example embodiment, methods and corresponding metrology modules and systems use stand-alone metrology tool(s) and track-integrated metrology tool(s) at distinct measurement patterns to address separately different aspects of variation among wafers.

Abstract: Target designs methods and targets are provided, in which at least some of the differentiation between target elements and their background is carried out by segmenting either of them. Directed self-assembly (DSA) processes are used to generate fine segmentation, and various characteristics of the polymer lines and their guiding lines are used to differentiate target elements from their background. Target designs and design principles are disclosed in relation to the DSA process, as well as optimization of the DSA process to yield high metrology measurement accuracy in face of production inaccuracies. Furthermore, designs and methods are provided for enhancing and using ordered regions of a DSA-produced polymer surface as target elements and as hard masks for production processes. The targets and methods may be configured to enable metrology measurements using polarized light to distinguish target elements or DSA features.

Abstract: A method and apparatus for process control in a lithographic process are described. Metrology may be performed on a substrate either before or after performing a patterning process on the substrate. One or more correctables to the lithographic patterning process may be generated based on the metrology. The patterning process performed on the substrate (or a subsequent substrate) may be adjusted with the correctables.

Abstract: Aspects of the present disclosure describe a target for use in measuring a relative position between two substantially coplanar layers of a device. The target includes periodic structures in first and second layers. Differences in relative position of the first and the second layers between the first and second periodic structures and the respective device-like structure can be measured to correct the relative position of the first and the second layers between the first and second periodic structures. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Abstract: Metrology targets, design files, and design and production methods thereof are provided. The metrology targets are hybrid in that they comprise at least one imaging target structure configured to be measurable by imaging and at least one scatterometry target structure configured to be measurable by scatterometry. Thus, the hybrid targets may be measured by imaging and scatterometry simultaneously or alternatingly and/or the measurement techniques may be optimized with respect to wafer regions and other spatial parameters, as well as with respect to temporal process parameters. The hybrid targets may be used to monitor process parameters, for example via comparative overlay measurements and/or high resolution measurements.

Abstract: A combined metrology mark, a system, and a method for calculating alignment on a semiconductor circuit are disclosed. The combined metrology mark may include a mask misregistration structure and a wafer overlay mark structure.

Abstract: Aspects of the present disclosure describe a target for use in measuring a relative position between two substantially coplanar layers of a device. The target includes periodic structures in first and second layers. Differences in relative position of the first and the second layers between the first and second periodic structures and the respective device-like structure can be measured to correct the relative position of the first and the second layers between the first and second periodic structures. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.