Abstract: An image signal processor includes a register and a disparity correction unit. The register stores disparity data obtained from a pattern image data that an image senor generates, and the image sensor includes a plurality of pixels, and each of the pixel includes at least a first photoelectric conversion element and a second photoelectric conversion element. The image sensor generates the pattern image data in response to a pattern image located at a first distance from the image sensor. The disparity correction unit corrects a disparity distortion of an image data based on the disparity data to generate a result image data, and the image senor generates the image data by capturing an object.

Abstract: The present invention relates to a composition or a method for treating or preventing irritable bowel syndrome. The present invention uses Atractylodes japonica rhizome extract, preferably the ethanol water solution extract of Atractylodes japonica rhizome, more preferably the 35-65 v/v % ethanol water solution extract of Atractylodes japonica rhizome for treating or preventing irritable bowel syndrome. Atractylodes japonica rhizome extract shows a surprising effect in suppressing visceral hypersensitivity or improving defecation abnormality caused by stress or bowel irritability.

Abstract: The present invention is an escalator handrail sterilizer which is installed close to an inlet or outlet of an escalator handrail, and cleans and sterilizes the handrail moving in or out. The sterilizer comprises a case which is prepared for surrounding the escalator handrail, a chemical spray unit which is prepared in one end inside the case to spray chemicals on the handrail moving in, an ultraviolet ray irradiation unit which is prepared in the other end inside the case to project ultraviolet rays on the chemical-sprayed handrail, a drying unit which dries the chemicals sprayed on the handrail, a control unit which controls the chemical spray unit, the UV irradiation unit and the drying unit, and a cover which is prepared in both ends of the case in order to prevent foreign materials from flowing into the case.

Abstract: A method and apparatus for generating an echo clock is described. An echo clock is an output strobe signal that selectively follows an input clock signal in a synchronous memory system and indicates when valid output data is available. The same clock signals used to change the state of an echo clock are used to output data from a memory buffer. The data buffer and echo clock buffer/generator are substantially identical in construction and operation, thereby ensuring a close correlation between a change in state of the echo clock and the availability of valid data. Such a memory provides matching of the echo clock transitions with that of the data signals on the data lines of the memory for any frequency range.

Abstract: An interconnection array is provided including a plurality of line conductors having segments substantially parallel to each other in each of two or more parallel regions such that the composite length of the segments essentially matches said length of the array; the line conductors crossing in one or more crossing regions located between the parallel regions so that no line conductor remains adjacent to the same pair of neighboring line conductors in any of segments of the array; wherein adjacent line conductors in the parallel regions are spaced one pitch from each other and wherein multiple line conductors are offset up or down no more than two pitches in each of the crossing regions.

Abstract: A semiconductor memory device divided into a number of main blocks each main block having a number of subblocks selects a single main block and enables the subblocks of the selected main block, so as to reduce the power consumptions. The semiconductor memory device includes a block selector for selecting one of the main blocks in response to row address signals, a number of first boost circuits for selecting the subblocks of the selected main block in response to the row address signals, and a number of second boost circuits adapted to be disabled in response to the row address signals.

Abstract: The present invention relates to a substrate voltage generator for a semiconductor device, comprising an oscillator for generating an oscillating signal to compensate the resistance value with temperature, a voltage pump driver for providing clock signals, a voltage pump for generating substate voltage, a level detector for detecting the substrate voltage, and a oscillating driver for providing the bias voltage, wherein the power consumption in the standby state of semiconductor devices can be reduced and the driving capacity is not variable even though the temperature is changed.

Abstract: The higher packing cells memory circuit includes a plurality word line drivers employing a plurality of word lines, a plurality of bit lines, and various decoders. Disclosed is the array method of the word line drivers, which can reduce the pitch between the word line drivers by, for example, arranging word lines in a group to provide a cross-over or to twist the word line is not continuously adjacent to the same neighboring word line, so that the layout of the semiconductor memory array may be easily accomplished. Moreover, the array method of other components of the memory array is suggested.

Abstract: A supply voltage converter circuit for use in reduced geometry high-density semiconductor memory devices, capable of reducing current consumption to as small a value as possible and achieving high-speed operation. The circuit includes a reference voltage generator, for generating a constant reference voltage, and a peripheral power-supply circuit, and array power-supply circuit for providing the internal supply voltage to the peripheral and array circuits, respectively.

Abstract: A sense amplifier driving circuit for controlling sense amplifiers of high density semiconductor memory device by turning-on/off a driving transistor connected between an external voltage Vcc terminal and a ground voltage Vss terminal, comprises a bias circuit including a MOS transistor being connected to the driving MOS transistor to form a current mirror circuit therewith which is controlled by a sense amplifier enable clock and a constant current source having a MOS transistor with a bias voltage of an intermediate level between Vcc and Vss being applied to its gate terminal. The bias circuit is connected to the gate terminal of the driving transistor to control the gate voltage of the driving transistor, thereby reducing the peak current of a sense amplifier driving signal. Further, the driving signals are generated in the waveform having a linear dual slope, resulting in a decrease in power-noise.

Abstract: A higher packing of cells in a memory circuit includes a plurality of word line drivers employing a plurality of word lines, a plurality of bit lines, and various decoders. Disclosed is the array method of the word line drivers, which can reduce the pitch between the word line drivers so that the layout of the semiconductor memory array may be easily accomplished. Moreover, the array method of other components of the memory array is suggested.

Abstract: An internal voltage converter in semiconductor integrated circuit, comprises an oscillator, a sub circuit including a buffer and a charge-pumping circuit and a power part, a main circuit including a buffer and a charge-pumping circuit and a power part, and a detector. A plurality of voltage converting stages are composed in parallel to be divided when operating so that the unnecesary consumption of the power is reduced in the case of providing the stand-by power and the stability of the internal power supply voltage is also improved.

Abstract: A semiconductor substrate bias circuit is disclosed which comprises: first and second substrate biasing means connected in parallel between the substrate and a ground node, for pumping the charges from said substrate to said ground node or in the reverse direction in order to bias said substrate; and a detecting means for selectively enabling said first and second substrate biasing means in accordance with the levels of the substrate bias voltage. The circuit of the present invention is capable of supplying adequate bias voltages depending on the various operating modes, reducing the standby current loss at a standby state, and is suitable for being installed on a VLSI semiconductor chip.

Abstract: A circuit for generating a back bias voltage for use in a semiconductor memory device is disclosed, wherein the back bias voltage is clamped within a desired voltage level. The circuit comprises an oscillator for generating a sequence of square waves having a specified frequency, a buffer adapted to be connected with the output of said oscillator and for buffering the output of said oscillator into the square waves having a level of a source supply voltage, a charge pump circuit for providing a back bias voltage by receiving the output of said buffer, and a clamping circuit adapted to be coupled in parallel between the output of said charge pump circuit and a ground level and for clamping within a specified range the back bias voltage being provided by said charge pump circuit in accordance with variations of said source supply voltage.