Abstract: A semiconductor device may include a gate stack that includes a first insulating pattern, a second insulating pattern adjacent to the first insulating pattern, a third insulating pattern adjacent to the second insulating pattern, a first conductive pattern between the first and second insulating patterns, and a second conductive pattern between the second and third insulating patterns, a channel layer that extends in the gate stack, a tunnel insulating layer on the channel layer, and a first data storage pattern and a second data storage pattern on the tunnel insulating layer. The first data storage pattern may include a first outer portion between the first and second insulating patterns, and a first inner portion on the first outer portion.

Abstract: A semiconductor device includes a plurality of gate electrodes spaced apart from each other in a vertical direction on a substrate, a plurality of channel structures respectively penetrating a plurality of gate electrodes and extending in the vertical direction, each comprising a channel layer having a stacked structure of a first oxide semiconductor channel layer and a second oxide semiconductor channel layer which have different conductivities, and a gate insulating layer disposed between the channel layer and each of the plurality of gate electrodes, and a plurality of bit lines disposed on the plurality of channel structures and respectively connected to the plurality of channel structures, and the gate insulating layer, the first oxide semiconductor channel layer, and the second oxide semiconductor channel layer are sequentially disposed.

Abstract: A method of manufacturing a semiconductor device is provided including the operations of forming a peripheral circuit structure including a substrate, circuit elements on the substrate, and interconnections on the circuit elements. The method includes forming a plate layer on the peripheral circuit structure, forming a preliminary stack structure by alternately stacking sacrificial layers and interlayer insulating layers on the plate layer in a first direction perpendicular to an upper surface of the plate layer, and patterning the stack structure to form a stepped structure to form patterned sacrificial layers and patterned interlayer insulating layers. The method includes forming deposition inhibition layers on exposed surfaces of the patterned interlayer insulating layers, forming selective deposition layers on exposed surfaces of the patterned sacrificial layers, forming channel structures penetrating through the preliminary stack structure in the first direction, and contacting the plate layer.

Abstract: A semiconductor device includes a conductive pattern, an insulating pattern, a channel film extending in a vertical direction inside a channel hole, a charge trap pattern between the conductive pattern and the channel film inside the channel hole, a tunneling dielectric film between the charge trap pattern and the channel film, and a blocking dielectric film extending between the conductive pattern and the charge trap pattern and between the insulating pattern and the tunneling dielectric film. The insulating pattern includes a first insulating pattern overlapping the conductive pattern in the vertical direction and a second insulating pattern protruding in the lateral direction from the first insulating pattern into the channel hole and toward the channel film. The first insulating pattern has a first dielectric constant, and the second insulating pattern has a second dielectric constant that is lower than the first dielectric constant.

Abstract: A variable resistance memory device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction and crossing the first conductive lines in a plan view, and cell structures respectively provided at crossing points of the first conductive lines and the second conductive lines in the plan view. Each of the cell structures includes a switching pattern, a variable resistance pattern, and a first electrode provided between the switching pattern and the first conductive line, the first electrode including carbon. Each of the first conductive lines includes an upper pattern including a metal nitride in an upper portion thereof. The upper pattern is in contact with a bottom surface of the first electrode.

Abstract: A resistive memory device includes a first conductive line extending in a first horizontal direction on a substrate, a plurality of second conductive lines separated from the first conductive line in a vertical direction and extending in a second horizontal direction intersecting with the first horizontal direction, on the substrate, a plurality of memory cells respectively connected between the first conductive line and one second conductive line selected from among the plurality of second conductive lines at a plurality of intersection points between the first conductive line and the plurality of second conductive lines, each of the plurality of memory cells including a selection device and a resistive memory pattern, and a bottom electrode shared by the plurality of memory cells, the bottom electrode having a variable thickness in the first horizontal direction, and including a top surface having a concave-convex shape.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device including a first conductive line on a substrate, memory cell structures stacked on the first conductive line, a second conductive line between the memory cell structures; and a third conductive line on the memory cell structures may be provided. Each of the plurality of memory cell structures includes a data storage material pattern, a switching material pattern, and a plurality of electrode patterns, at least one of the electrode patterns includes at least one of carbon material layer or a carbon-containing material layer, and the at least one of the electrode patterns includes a first region doped with a nitrogen and a second region that is not doped with the nitrogen, or is doped with the nitrogen at a first concentration lower than a second concentration of the nitrogen in the first region.

Abstract: A method of manufacturing a semiconductor device includes forming a molded structure of stacked and alternating interlayer insulating layers and sacrificial layers on a lower structure, forming a hole through the molded structure, forming recess regions in the sacrificial layers of the molded structure, respectively, by removing a portion of the sacrificial layers, exposed through the hole, from side surfaces of the sacrificial layers, sequentially forming a preliminary blocking pattern and a charge storage pattern in each of the recess regions, sequentially forming a tunneling layer and a channel layer in the hole, forming trenches penetrating through the molded structure, such that the trenches extend in a line shape, removing the sacrificial layers exposed by the trenches, such that the preliminary blocking pattern is exposed, and oxidizing the preliminary blocking pattern, after removing the sacrificial layers, such that a blocking pattern is formed.

Abstract: A semiconductor device and a method of manufacturing the same. The method may include: forming a mold stack that includes a plurality of insulating layers alternately arranged with a plurality of sacrificial layers; forming a preliminary pad portion by sequentially patterning the mold stack; forming a cell contact hole that extends through the preliminary pad portion and the sacrificial layer portions; forming a first extension portion and a plurality of second extension portions by laterally expanding the preliminary pad portion and the sacrificial layer portions; forming a first insulating liner and a sacrificial ring pattern in the first extension portion; forming an oxide liner and an insulating ring pattern in the second extension portions; forming a sacrificial plug within the cell contact hole; and replacing the sacrificial layers with gate electrodes and replacing the preliminary pad portion, the first insulating liner, and the sacrificial ring pattern with a pad portion.

Abstract: A method for manufacturing a semiconductor device includes forming a first pattern structure having a first opening on a lower structure comprising a semiconductor substrate. The first pattern structure includes a stacked pattern and a first spacer layer covering at least a side surface of the stacked pattern. A first flowable material layer including a SiOCH material is formed on the first spacer layer to fill the first opening and cover an upper portion of the first pattern structure. A first curing process including supplying a gaseous ammonia catalyst into the first flowable material layer is performed on the first flowable material layer to form a first cured material layer that includes water. A second curing process is performed on the first cured material layer to form a first low-k dielectric material layer. The first low-k dielectric material layer is planarized to form a planarized first low-k dielectric material layer.

Abstract: A method of manufacturing a variable resistance memory device may include: forming a memory cell including a variable resistance pattern on a substrate; performing a first process to deposit a first protective layer covering the memory cell; and performing a second process to deposit a second protective layer on the first protective layer. The first process and the second process may use the same source material and the same nitrogen reaction material, and a nitrogen content in the first protective layer may be less than a nitrogen content in the second protective layer.

Abstract: A method of fabricating a variable resistance memory device that includes forming a plurality of memory cells on a substrate. Each of the plurality of memory cells in a switching device and a variable resistance pattern. A capping structure is formed that commonly covers lateral side surfaces of the plurality of memory cells. An insulating gapfill layer is formed that covers the capping structure and fills a region between adjacent memory cells of the plurality of memory cells. The forming of the capping structure includes forming a second capping layer including silicon oxide that covers the lateral side surfaces of the plurality of memory cells. At least a partial portion of the second capping layer is nitrided by performing a first decoupled plasma process to form a third capping layer that includes silicon oxynitride.

Abstract: A resistive memory device includes a first conductive line extending in a first horizontal direction on a substrate, a plurality of second conductive lines separated from the first conductive line in a vertical direction and extending in a second horizontal direction intersecting with the first horizontal direction, on the substrate, a plurality of memory cells respectively connected between the first conductive line and one second conductive line selected from among the plurality of second conductive lines at a plurality of intersection points between the first conductive line and the plurality of second conductive lines, each of the plurality of memory cells including a selection device and a resistive memory pattern, and a bottom electrode shared by the plurality of memory cells, the bottom electrode having a variable thickness in the first horizontal direction, and including a top surface having a concave-convex shape.

Abstract: A variable resistance memory device includes first conductive lines extending in a first direction, second conductive lines extending in a second direction and crossing the first conductive lines in a plan view, and cell structures respectively provided at crossing points of the first conductive lines and the second conductive lines in the plan view. Each of the cell structures includes a switching pattern, a variable resistance pattern, and a first electrode provided between the switching pattern and the first conductive line, the first electrode including carbon. Each of the first conductive lines includes an upper pattern including a metal nitride in an upper portion thereof. The upper pattern is in contact with a bottom surface of the first electrode.

Abstract: A variable resistanvce memory device may include a plurality of first conductive lines extending in a first direction, a plurality of second conductive lines extending in a second direction, a plurality of memory cells, each memory cell at a respective intersection, with respect to a top down view, between a corresponding one of the first conductive lines and a corresponding one of the second conductive lines, each memory cell comprising a variable resistance structure and a switching element sandwiched between a top electrode and a bottom electrode, and a first dielectric layer filling a space between the switching elements of the memory cells. A top surface of the first dielectric layer is disposed between bottom and top surfaces of the top electrodes of the memory cells.

Abstract: A method of fabricating a memory device includes forming word lines and cell stacks with gaps between the cell stacks, forming a lower gap-fill insulator in the gaps, forming an upper gap-fill insulator on the lower gap-fill insulator, curing the lower gap-fill insulator and the upper gap-fill insulator to form a gap-fill insulator, and forming bit lines on the cell stacks and the gap-fill insulator. The lower gap-fill process may be performed using a first source gas that includes first and second precursors, and the upper gap-fill process may be performed using a second source gas that includes the first and second precursors, a volume ratio of the first precursor to the second precursor in the first source gas may be greater than 15:1, and a volume ratio of the first precursor to the second precursor in the second source gas may be less than 15:1.

Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device including a first conductive line on a substrate, memory cell structures stacked on the first conductive line, a second conductive line between the memory cell structures; and a third conductive line on the memory cell structures may be provided. Each of the plurality of memory cell structures includes a data storage material pattern, a switching material pattern, and a plurality of electrode patterns, at least one of the electrode patterns includes at least one of carbon material layer or a carbon-containing material layer, and the at least one of the electrode patterns includes a first region doped with a nitrogen and a second region that is not doped with the nitrogen, or is doped with the nitrogen at a first concentration lower than a second concentration of the nitrogen in the first region.

Abstract: A method of fabricating a variable resistance memory device that includes forming a plurality of memory cells on a substrate. Each of the plurality of memory cells in a switching device and a variable resistance pattern. A capping structure is formed that commonly covers lateral side surfaces of the plurality of memory cells. An insulating gapfill layer is formed that covers the capping structure and fills a region between adjacent memory cells of the plurality of memory cells. The forming of the capping structure includes forming a second capping layer including silicon oxide that covers the lateral side surfaces of the plurality of memory cells. At least a partial portion of the second capping layer is nitrided by performing a first decoupled plasma process to hum a third capping layer that includes silicon oxynitride.

Abstract: A method of manufacturing a variable resistance memory device includes: forming an array of memory cells on a substrate, each memory cell including a variable resistance structure and a switching element; and forming a sidewall insulating layer covering a sidewall of the switching element. The forming the sidewall insulating layer includes: a preliminary step of supplying a silicon source to an exposed sidewall of the switching element; and a main step of performing a process cycle a plurality of times, the process cycle comprising supplying the silicon source and supplying a reaction gas, A time duration of the supplying the silicon source in the preliminary step is longer than a time duration of the supplying the silicon gas in the process cycle in the main step.

Abstract: A method for manufacturing a semiconductor device includes forming a first pattern structure having a first opening on a lower structure comprising a semiconductor substrate. The first pattern structure includes a stacked pattern and a first spacer layer covering at least a side surface of the stacked pattern. A first flowable material layer including a SiOCH material is formed on the first spacer layer to fill the first opening and cover an upper portion of the first pattern structure. A first curing process including supplying a gaseous ammonia catalyst into the first flowable material layer is performed on the first flowable material layer to form a first cured material layer that includes water. A second curing process is performed on the first cured material layer to form a first low-k dielectric material layer. The first low-k dielectric material layer is planarized to form a planarized first low-k dielectric material layer.