Abstract: A control store holding a large number of instruction words is accessed by a sequence of instruction addresses. An intercooperating system uses a test condition select logic unit and a next address select logic unit are combined with address sequence error detection logic in order to develop an error flag signal should there be some error in the sequence of the actual instruction address data supplied to the control store.

Abstract: A wide ROM-PROM memory is structured of multiple memory chips in parallel plus an auxiliary parity memory chip to hold parity bits for each corresponding addressable location in each memory chip. Sensing means is provided to check parity of data bits read from each memory location to verify integrity of the read-out.

Abstract: A parity detection scheme for a wide memory structure of RAM memory chips provides an auxiliary RAM parity memory chip to store parity data for each corresponding input line of each memory chip corresponding for each address of each memory chip. This parity data is compared to comparable parity data which is read-out of any corresponding address of each of said memory chips.

Abstract: A parity checking system for establishing integrity of data transfer on a wide bus. Each set of "4" bus lines of a multiple line bus is passed from a driver chip to a corresponding receiver chip. An added parity driver chip senses each corresponding bit line of each driver chip to develop a set of four parity signals for comparison with corresponding parity signals from each corresponding bit line of each one of a set of receiver chips. Any discrepancy will generate a parity error signal.

Abstract: A programmable unit for attachment to a work-station whereby power to the work-station will be shut off after a pre-set time-period, unless work-station activity occurs before the outset of the time-period, when the pre-set time-period will initiate again.

Abstract: Multi-phase subroutine control apparatus for use in a data processing system which provides for the concurrent execution of a plurality of tasks in a multiprogramming and multiprocessing environment. Subroutine control operations are staged so as to share common hardware in a manner which in effect provides a plurality of phased concurrently operating subroutine control circuits wherein each circuit provides control for a different one of a plurality of concurrently executing tasks. The common subroutine hardware includes a multi-level stack for each task and a fast access return address register which permits a return address to be rapidly made available when required during execution of a task.

Abstract: A pipelined microprogrammed data processing system is provided having a three-stage pipelined architecture implemented so as to in effect provide for the execution of a plurality of microinstructions using three separate processors operating 120 degrees out of phase with one another and sharing the same physical hardware. Synchronized microinstruction tasking and dynamic resource allocation are also provided in the system to provide both multiprogramming and multiprocessing on a microinstruction level.

Abstract: A microprogrammed data processing system is provided in which each high level instruction is performed by one or more tasks, each task being in turn performed by executing one or more task microinstructions in a microprogrammed manner. Dynamic resource allocation is provided by employing a plurality of dynamically allocatable registers whose free and use states are continuously monitored in an allocation register. The outputs of the allocation register are used as an address for a register allocation memory which is mapped so as to identify a particular group of free registers which are available for assignment for each new task in response to the allocation register address.

Abstract: Multi-phase subroutine control apparatus for use in a data processing system which provides for the concurrent execution of a plurality of tasks in a multiprogramming and multiprocessing environment. Subrouting control operations are staged so as to share common hardware in a manner which in effect provides a plurality of phased concurrently operating subroutine control circuits wherein each circuit provides control for a different one of a plurality of concurrently executing tasks. The common subroutine hardware includes a multi-level stack for each task and a fast access return address register which permits a return address to be rapidly made available when required during execution of a task.

Abstract: Subroutine control apparatus for providing shared subroutine control for a plurality of executing tasks. Multiple levels of subroutine entry are provided for each task by employing a plurality of selectably accessible stacks, one for each task, along with corresponding pointer registers. These provide storage for a plurality of return addresses as required for each task during task performance. In addition, an updatable significantly faster access register is provided for each task for storing its most recent return address so as to permit return addresses to be rapidly made available when an executing task reaches the end of a subroutine.

Abstract: A digital data processor operates at a microinstruction level in a multiprocessing and multiprogramming environment. The processor includes multi-phase subroutine control apparatus which provides for multiple levels of subroutine entry for a plurality of concurrently executing tasks, while also permitting the tasks to share the same subroutines. Tasks and subroutine control operations are staged to employ common hardware in a manner which provides the effect of a plurality of separate processors operating concurrently on different tasks in a multi-phased manner.

Abstract: A microprogrammed data processing system is provided in which each high level instruction is performed by one or more tasks, each task being in turn performed by executing one or more task microinstructions in a microprogrammed manner. Dynamic resource allocation and task synchronization are additionally provided along with a three-stage pipelined architecture so as to provide both multiprogramming and multiprocessing on a microinstruction level.

Abstract: Register selection apparatus which includes a plurality of specially mapped programmable memories each addressed by a respective portion of an updatable allocation register which indicates the free and assigned states of a plurality of registers. The resulting memory words read out from the memories are applied to a plurality of multiplexers for identifying a particular predetermined group of registers as being available for assignment. The memory words also provide signals for use in determining whether a sufficient number of free registers are currently available for assignment.

Abstract: Apparatus which detects and corrects both transient and single bit memory read errors while selectively logging only solid (that is, hardware-related) single bit memory read errors. Each of a plurality of memory modules directly transmits uncorrected memory data to a processor memory control while also providing for automatic local restoring of corrected data back into the memory address which produced the single bit error. The processor memory control provides its own error detection and correction employing syndrome generating and decoding circuitry which detects both multiple and single bit errors. Multiple bit errors are not corrected, but merely brought to the attention of the processor. Single bit errors are corrected, but only those which are found to most likely be solid errors are logged. A solid single bit error is recognized by detecting when two single bit errors having the same memory address occur consecutively.

Abstract: Apparatus which detects and corrects both transient and single bit memory read errors while selectively logging only solid (that is, hardware-related) single bit memory read errors. Each of a plurality of memory modules directly transmits uncorrected memory data to a processor memory control while also providing for automatic local restoring of corrected data back into the memory address which produced the single bit error. The processor memory control provides its own error detection and correction which detects both multiple and single bit errors. Multiple bit errors are not corrected, but are merely brought to the attention of the processor. Single bit errors are corrected but only those which are found to most likely be solid errors are logged. A solid single bit error is recognized by detecting when two single bit errors having the same memory address occur consecutively.

Abstract: Improved means and methods for providing highly flexible microinstruction sequencing in a microprogrammed digital data processing system particularly with regard to the handling of specialized types of sequencing situations such as are involved in wait-loop and repeat situations. The microprogramming control system is implemented using a plurality of programmable read only memories storing control words chosen so as to provide for microinstruction sequencing in a manner which in the first instance assumes that no branching possibilities are present, even though one or more branching possibilities may in fact be present in the microinstruction flow path, thereby permitting very fast microinstruction sequencing when the assumed sequencing is correct.

Abstract: A microprogrammed digital computer employing a plurality of programmable read only memories containing stored control words which are specially chosen so as to provide for microinstruction sequencing in a manner which in the first instance assumes that no branching possibilities are present, even though one or more branching possibilities may in fact be present in the microinstruction flow path. The correctness of microinstruction sequencing is monitored concurrently with the execution of a microinstruction during each cycle for which a branching decision is required. When an incorrect assumed sequence is detected, correction is provided using microinstruction indexing and inhibiting signals which are selectively provided in response to the states of selected system conditions during the cycle.